TEC-ED & TEC-SW Final Presentation Days - December 2016
from
Tuesday 6 December 2016 (08:00)
to
Wednesday 7 December 2016 (18:15)
Monday 5 December 2016
Tuesday 6 December 2016
08:00
Registration
-
Kathleen Gerlo
(
ESA/ESTEC - Software Systems Division
)
Bertilla Sinka
(
ESTEC
)
Registration
Kathleen Gerlo
(
ESA/ESTEC - Software Systems Division
)
Bertilla Sinka
(
ESTEC
)
08:00 - 08:30
Room: Newton 2
08:30
Introduction
Introduction
08:30 - 08:45
Room: Newton 2
08:45
Schedulability Analysis Techniques and Tools for Cached and Multicore Processors
-
Panagiotis Katsaros
(
CERTH
)
Schedulability Analysis Techniques and Tools for Cached and Multicore Processors
Panagiotis Katsaros
(
CERTH
)
08:45 - 09:30
Room: Newton 2
09:30
Definition and Design of software components for LEON3FT Microcontroller and LEON-REX Instruction Set Architecture
-
Daniel Cederman
(
Cobham Gaisler AB
)
Definition and Design of software components for LEON3FT Microcontroller and LEON-REX Instruction Set Architecture
Daniel Cederman
(
Cobham Gaisler AB
)
09:30 - 10:15
Room: Newton 2
10:15
OBC Mass Memory (Solid State mass Memory Board/Module Integrated in OBC)
-
Patrick Sandin
(
RUAG Space AB
)
Dietmar Walter
(
DSI
)
Glenn Johnson
(
SciSys
)
OBC Mass Memory (Solid State mass Memory Board/Module Integrated in OBC)
Patrick Sandin
(
RUAG Space AB
)
Dietmar Walter
(
DSI
)
Glenn Johnson
(
SciSys
)
10:15 - 11:00
Room: Newton 2
11:00
Coffee Break
Coffee Break
11:00 - 11:30
Room: Newton 2
11:30
CLP: Control Loop Processor, Architectural Design, Verification and FPGA prototypes
-
Marco Ruiz
(
SABCA
)
CLP: Control Loop Processor, Architectural Design, Verification and FPGA prototypes
Marco Ruiz
(
SABCA
)
11:30 - 12:15
Room: Newton 2
12:15
Deploying Plug and Play Avionics
-
Richard Melvin
(
SciSys
)
Deploying Plug and Play Avionics
Richard Melvin
(
SciSys
)
12:15 - 13:00
Room: Newton 2
13:00
Lunch Break
Lunch Break
13:00 - 14:00
Room: Newton 2
14:00
Extensions and Validation of Virtual Platform for complex System-on-Chip and IP Cores Design for Space
-
Alberto Ferrazzi
(
Terma
)
Extensions and Validation of Virtual Platform for complex System-on-Chip and IP Cores Design for Space
Alberto Ferrazzi
(
Terma
)
14:00 - 14:45
Room: Newton 2
14:45
Space Fibre IP core
-
Felix Siegle
(
Cobham Gaisler AB
)
Space Fibre IP core
Felix Siegle
(
Cobham Gaisler AB
)
14:45 - 15:30
Room: Newton 2
15:30
Coffee Break
Coffee Break
15:30 - 16:00
Room: Newton 2
16:00
DMON and the AGGA 4
-
Michael Ryan
(
O.C.E. Technology
)
DMON and the AGGA 4
Michael Ryan
(
O.C.E. Technology
)
16:00 - 16:45
Room: Newton 2
16:45
LLVM compiler for in flight SW development and validation process
-
Emil Vassev
(
LERO
)
LLVM compiler for in flight SW development and validation process
Emil Vassev
(
LERO
)
16:45 - 17:30
Room: Newton 2
Wednesday 7 December 2016
08:00
Registration
-
Bertilla Sinka
(
ESTEC
)
Kathleen Gerlo
(
ESA/ESTEC - Software Systems Division
)
Registration
Bertilla Sinka
(
ESTEC
)
Kathleen Gerlo
(
ESA/ESTEC - Software Systems Division
)
08:00 - 08:30
Room: Newton 2
08:30
Introduction
Introduction
08:30 - 08:45
Room: Newton 2
08:45
TASTE Multicore
-
Jérôme Hugues
(
ISAE SUPAERO
)
Claire Pagetti
(
ONERA
)
TASTE Multicore
Jérôme Hugues
(
ISAE SUPAERO
)
Claire Pagetti
(
ONERA
)
08:45 - 09:30
Room: Newton 2
09:30
Improvement of the OSRA SCM Model Editor
-
Goulwen Le Fur
(
Obeo
)
Andreas Jung
(
ESA/ESTEC
)
Improvement of the OSRA SCM Model Editor
Goulwen Le Fur
(
Obeo
)
Andreas Jung
(
ESA/ESTEC
)
09:30 - 10:15
Room: Newton 2
10:15
Benchmarking Autonomous Robotics Controllers (NPI Activity)
-
Pablo Muñoz
(
University of Alcalá
)
Benchmarking Autonomous Robotics Controllers (NPI Activity)
Pablo Muñoz
(
University of Alcalá
)
10:15 - 11:00
Room: Newton 2
11:00
Coffee Break
Coffee Break
11:00 - 11:30
Room: Newton 2
11:30
SpaceWire Electrical Testing
-
Brice Dellandrea
(
Thales Alenia Space - France
)
SpaceWire Electrical Testing
Brice Dellandrea
(
Thales Alenia Space - France
)
11:30 - 12:15
Room: Newton 2
12:15
Multi-threaded processor for space applications
-
Chris Jesshope
Martin Daněk
(
Daiteq s.r.o.
)
Multi-threaded processor for space applications
Chris Jesshope
Martin Daněk
(
Daiteq s.r.o.
)
12:15 - 13:00
Room: Newton 2
13:00
Lunch Break
Lunch Break
13:00 - 14:00
Room: Newton 2
14:00
Verification of Computer-Controlled Systems
-
Elena Alaña Salazar
(
GMV
)
Verification of Computer-Controlled Systems
Elena Alaña Salazar
(
GMV
)
14:00 - 14:45
Room: Newton 2
14:45
Catalogue for System and Software Properties - CatSY
-
Victor Bos
(
SSF
)
Catalogue for System and Software Properties - CatSY
Victor Bos
(
SSF
)
14:45 - 15:30
Room: Newton 2
15:30
Catalogue for System and Software Properties - CSSP
-
Panagiotis Katsaros
(
AUTh
)
Simon Bliudze
(
EPFL
)
Catalogue for System and Software Properties - CSSP
Panagiotis Katsaros
(
AUTh
)
Simon Bliudze
(
EPFL
)
15:30 - 16:15
Room: Newton 2
16:15
Coffee Break
Coffee Break
16:15 - 16:45
Room: Newton 2
16:45
Enabling FDIR design through diagnosability and recoverability analysis
-
Benjamin Bittner
(
Fondazione Bruno Kessler
)
Enabling FDIR design through diagnosability and recoverability analysis
Benjamin Bittner
(
Fondazione Bruno Kessler
)
16:45 - 17:30
Room: Newton 2
17:30
Consolidation of COMPASS tools
-
Marco Bozzano
(
Fondazione Bruno Kessler
)
Harold Bruintjes
(
RWTH Aachen University
)
Consolidation of COMPASS tools
Marco Bozzano
(
Fondazione Bruno Kessler
)
Harold Bruintjes
(
RWTH Aachen University
)
17:30 - 18:15
Room: Newton 2