|08:00||Registration / Coffee|
|08:30||European Space Agency||Roland Weigand||Welcome – Introduction to and history of the NGMP and GR740 development.||After the MA31750, the first space microprocessor developed in Europe in the early 90s with MIL-STD-1750A Instruction Set Architecture (ISA), the transition to the open standard SPARC ISA was made, and several generations of SPARC microprocessors have been developed under ESA authority in the 90s and early 2000s. Today, including many FPGA implementations, several thousands of SPARC processors have been flying in space.
To prepare the transition to a multi-core, higher performance processor, the preliminary GINA (Giga Instruction New Architecture) study, using a quad-core LEON3, was completed in 2006.
The development of the GR740 was initiated in 2009 under the code name Next Generation Microprocessor (NGMP) with Cobham Gaisler, and conducted under various ESA (TRP/GSTP) contracts and own investment. Early prototypes in commercial technology and evaluation boards were made available in 2013.
The design was ported as of 2014 to the newly available C65SPACE 65 nm ASIC platform from ST Microelectronics, EM prototypes and evaluation boards have become available in Q2/2016. Thereafter, flight parts have been developed, packaged, functionally and radiation tested, and space qualification is currently in progress.
The NGMP/GR740 development was funded by various ESA programmes (TRP/GSTP/EOPP), as well as internal industry investment.
The chip development is accompanied by numerous activities to develop and improve the software ecosystem (compiler, operating system, hypervisor, timing analysis tools etc.).
|08:45||Data Device Corporation (DDC)||Robert Hillman||SCS3740 3U SpaceVPX Single Board Computer using GR740 Processor||Data Device Corporation (DDC) Microelectronics business unit (formerly part of Maxwell Technologies) is a legacy supplier of Single Board Computers (SBCs) and rad hard components for Space. DDC’s legacy SBC, the SCS750 which is Power PC based, is TRL-9 and has been used on a number of European programs. DDC has expanded its SBC offerings with a high performance, SWaP (size, weight and power) optimized 3U SpaceVPX card based on the GR740. This SBC, the SCS3740 SBC, has been designed with all space qualified, ceramic hermetic components including 128Mbyte SDRAM, 4Mbyte EEPROM, 32Gbyte FLASH NAND, power conversion/clocks and an RTAX FPGA. DDC will present the key board features, review the SBC block diagram, discuss our general tradeoffs and challenges, as well introduce a new Development Kit platform to accelerate system integration.|
|09:10||Cobham Gaisler||Magnus Hjorth||GR740 Development Status||The GR740 has been developed in a series of ESA activities and flight models are currently in development. The presentation will provide a brief overview of the development up to the final architecture and provide a status update on the currently on-going work.|
|09:40||Airbus Defense & Space - Toulouse||Paul DUTEIS, Roland BROCHARD, Sylvain TIBERIO||GENEVIS, a Vision-Based Navigation Solution Integrated on a Single LEON4 Core||"""With the GENEVIS study, Airbus DS has successfully integrated its vision-based navigation algorithms for real-time applications on a single LEON4 core:
- METIS, a model-based tracker, for autonomous rendezvous applications
- THEMIS and Discover, a feature tracker and a landmark matching technique, for precise landing applications such as PILOT
- An in-house implementation of a Schmidt EKF in UD form
In particular, challenging software blocks such as correlation and ray tracing were ported on the GR740 under real-time constraints."""
|10:05||Thales Alenia Space – Italy, Competence Center Electronics||Gianluca Aranci||Thales Alenia Space in Italy experience with GR740||Thales Alenia Space in Italy started to use GR740 since 2016. First Engineering Model board has been designed in 2016 and completed in 2017 with first silicon version of the device.
On these grounds, TAS has based on the GR740 processor the IPAC advanced Platform Computer System. The presentation reports experience matured on the field, with positive and negative feedback both on hardware and software aspects. Recommendations for the future are also indicated.
|11:00||Barcelona Supercomputing Centre, Airbus Defense & Space - Toulouse||BSC: Eduardo Quiñones; ADS: Franck Wartel||Extrae: an OpenMP-compatible performance monitoring tool for the GR740||OpenMP is a very promising parallel programming model for modern embedded multicores processors and SoCs , thanks to its great expressiveness and guaranteed performance. However OpenMP framework does not include a performance monitoring tool for characterizing the parallel execution. To solve this limitation, BSC have developed Extrae, a powerful performance monitoring tool used in the HPC for tuning the parallel execution, and ported it to GR740 in the scope of the HP4S project.|
|11:25||(*) Thales Alenia Space, (+) Cobham Gaisler, (†) Airbus Defense and Space France, (‡) European Space Agency, ESTEC, Netherlands||Patricia Lopez Cueva (*)||“CoRA-RDHC MIDDLEWARE: a software execution platform for cora-rhdc oN-bOARD computer”||“Compact Reconfigurable Avionics – Reconfigurable Data Handling Core” (CoRA-RHDC) is a TRP R&D study funded by ESA.
The main objective of the whole RHDC activity is to develop a highly reconfigurable On-Board Computer together with its software execution platform allowing versatility during space mission phases using state of the art components: GR740/GR718 and BRAVE NG-MEDIUM FPGAs interconnected using SpaceVPX.
The RDHC Middleware software execution platform provides both classical (Spacewire, UART, OBT…) and reconfiguration data handling services. It runs on RTEMS-5 SMP, embeds low-level drivers, a reconfiguration engine and the CNES PUS library.
The presentation will provide user feedback on the usage of GR740 to handle both reconfigurable NG-MEDIUM FPGA and payload link interaction in the context of the CoRA-RDHC study.
|11:50||GMV Poland||Laura Gouveia||GNSS Software Receiver||In a ESA commissioned activity named GNSSW-LEON4, it was implement an on-board Software Defined Radio GNSS (SDR-GNSS) receiver on a GR-740 on-board computer using RTEMS 5 with SMP.
At a first phase an optimized SDR-GNSS was ported to RTEMS 5 with SMP using the 4 cores of the GR740 and on a second phase it was ported to a TSP paradigm using AIR hypervisor.
The porting an already optimized GNSS- SDR application into SMP and later into the TSP paradigm with also SMP at same time brought several challenges, specially too ensure the execution of all tracking software within a temporal deadline.
|12:15||GMV Spain / Portugal||Laura Gouveia||Application of AIR as LEON4 hypervisor in Space Activities and Use Cases||Since the availability of the NGMP and up until now using the latest GR740 development board, the AIR TSP (Time Space partitioning) has been developed to fully use GR740 features.
As a result it has been applied in several activities demonstrating multi-core usage, TSP with SMP usage and also emulation of LEON4 with TSP.
|12:40||RUAG Space||Lars-Göran Green||GR740 Reference Design||The “Reference Design and Basic Software for a Single Board Computer based on GR740” is a technology development activity funded by ESA, with the title reflecting the main objective of the development in the activity. The Reference Design will be available for European space users. The work will also result in an Elegant Breadboard and Basic Software to be verified on a functional and performance level, as well as a qualification test plan for future space qualification.|
|14:00||SCISYS||Daniel Townson||Visual Odometry on the GR740||SCISYS has already produced a robust Visual Odometery solution for use on ESA’s LEON2 based ExoMars rover. SCISYS is currently undergoing a breadboarding activity to assess the suitability of VisLoc for use on the GR740 Sample-Fetch Rover. This work documents the important role the GR740 has played in achieving this missions critical objectives.|
|14:25||Airbus Defense & Space - Bremen||Alexander Hrusovsky (Airbus Defence and Space), Tobias Hartmann (Airbus Defence and Space)||Next Generation Data Handling System OBC-SA/SPINAS||It can be agreed that the next missions for mankind in space (race to the moon, and beyond) will be based on mission and safety critical HW and SW solutions. The GR740 is designed to fulfil this part – embedded in an expandable architecture and accompanied by a solid operating system foundation. The NG DHS will not only be a single computing board but a scalable platform. The GR740 is the safety critical component and the basis for the Integrated Modular Architecture (IMA).|
|14:50||ENEA AB Romania||Cristian Trohin||Paravirtualization on LEON4/GR740||ENEA has developed two projects with ESA and other partners to achieve the paravirtualization of RTEMS, FreeRTOS and Linux on LEON4/GR740 based hardware, using XtratuM hypervisor. The TSPL project aimed to demonstrate the Time and Space Partitioning capabilities of XtratuM when RTEMS and Linux are executed on the same platform, while the RTXM project handled the porting of FreeRTOS on XtratuM over SPARC, as well as developing tracing tools for RTEMS and FreeRTOS based on GRMON/RTEMS trace linker.|
|15:15||Embedded Brains||Dr. Matthias Göbel, Sebastian Huber||Bridging Open Source and Critical Space Applications||The open source real-time operating system RTEMS supports right now the GR740 quad-core platform with a rich feature set. How can it be made fit to allow its use in critical space applications? Once made available how can the RTEMS Project keep or increase the achieved quality level?|
|16:10||Department of Astrophysics, University of Vienna||Armin Luntzer||State of the University of Vienna's flight operating system on the GR740||The Department of Astrophysics at the University of Vienna is a provider of payload instrument flight software. An outcome of the SW development activities is a SMP-capable operating system with MMU support. We present an overview of the current state of the GR740 port and benchmark results for astrophysical on-board data processing scenarios.|
|16:35||Fent ISS||Paco Gómez Molinero||XtratuM: A space qualified Hypervisor for LEON-based Computers||The development roadmap and qualification activities for the XtratuM hypervisor in LEON processors will be presented. The space missions already commited to use XtratuM with LEON-based computers will be presented including multicore implementations.|
|17:20||European Space Agency||Roland Weigand||Conclusion|
|17:30||End of Workshop|