Name: SEFUW: SpacE FPGA Users Workshop, 2nd Edition
Start: 2014-09-16T09:30:00+02:00
End: 2014-09-18T14:00:00+02:00
Location: European Space Research and Technology Centre (ESTEC)

Monday 15 September 2014
Tuesday 16 September 2014

09:30 Registration and Early Morning Networking Break sponsored by Thales Communications & Security
Registration and Early Morning Networking Break sponsored by Thales Communications & Security
09:30 - 10:00
Room: Newton 2
10:00 Welcome - David Dangla (CNES) David Merodio Codinachs (ESA)
Welcome
- David Dangla (CNES)
- David Merodio Codinachs (ESA)
10:00 - 10:15
Room: Newton 2 Welcome by David Dangla (CNES) and David Merodio Codinachs (ESA)
10:15
10:15 - 11:30
Room: Newton 2
Contributions

10:15 RHBD FPGA AT40K Family - Valerie Briot (ATMEL)

11:05 IDS/FIGARO Enhancement Program - Yohann Bricard (ATMEL Nantes SAS)
11:30
11:30 - 13:00
Room: Newton 2
Contributions

11:30 Analysis and Mitigation of SEUs on SRAM-based FPGAs using the VERI-Place tool - Luca Sterpone (Politecnico di Torino)

12:00 Role of Fault Injection in Digital Design for Space - Hipolito Guzman Miranda (Universidad de Sevilla) Miguel A. Aguirre (Universidad de Sevilla)

12:30 SETs Broadening Tuning: A Place and Route Approach - Luca Sterpone (Politecnico di Torino)
13:00 Networking Luncheon
Networking Luncheon
13:00 - 14:00
14:00
14:00 - 15:30
Room: Newton 2
Contributions

14:00 FPGA use in future space rover navigation - George Lentaris (National Technical University of Athens, Greece)

14:30 Dynamically Reconfigurable Hardware for Resource Efficiency and Fault Tolerance in Space Applications - Dario Cozzi (Bielefeld University)

15:00 From Rosetta to current developments using FPGAs for scientific space missions - Tobias Lange (IDA, TU Braunschweig)
15:30 Networking Coffee Break sponsored by Thales Communications & Security
Networking Coffee Break sponsored by Thales Communications & Security
15:30 - 16:00
Room: Newton 2

16:00

16:00 - 18:00
Room: Newton 2

20:00 SEFUW Dinner
SEFUW Dinner
20:00 - 22:30
Room: - SEFUW dinner is planned on September 16th in "Iets Anders in Bistro Bardot". Price: 42.5 EUR The price includes a 3 course menu and drink arrangement. The restaurant is situated in Pickeplein 4 - 2202 CK Noordwijk.
Wednesday 17 September 2014
08:50 SEFUW Intro - Opening Remarks - David Merodio Codinachs (ESA) David Dangla (CNES)
SEFUW Intro - Opening Remarks
- David Merodio Codinachs (ESA)
- David Dangla (CNES)
08:50 - 09:00
Room: Newton 2 Opening remarks by David Dangla (CNES) and David Merodio Codinachs (ESA)
09:00
09:00 - 10:40
Room: Newton 2
Contributions

09:00 Update on Microsemi Radiation Tolerant FPGAs and Space System Manager Products - Ken O'Neill (Microsemi)

10:00 Xilinx Space Grade Packaging & Development Updates - Daniel Elftmann (Xilinx)
10:40 Networking Coffee Break sponsored by Thales Communications & Security
Networking Coffee Break sponsored by Thales Communications & Security
10:40 - 11:10
Room: Newton 2
11:10
11:10 - 13:10
Room: Newton 2
Contributions

11:10 Design experience and verification methods using the latest Microsemi RTAX FPGAs - Ottmar Ried (Airbus DS GmbH)

11:40 General use of FPGAs in Thales Alenia Space - Gregory Grimonet (Thales Alenia Space)

12:10 FPGA in SODERN recent projects for space applications - Christophe Pourrier (SODERN)

12:40 SRAM-based FPGAS for Space Applications: Current Projects @INAF - Monica Alderighi (INAF, Italy)
13:10 Networking Luncheon
Networking Luncheon
13:10 - 14:10
14:10
14:10 - 14:40
Room: Newton 2
Contributions

14:10 An Orbit-specific Fault-injector to Assess Fault-mitigation Strategies in Space FPGAs - Giovanni Beltrame (Polytechnique Montreal)
14:40
14:40 - 15:55
Room: Newton 2
Contributions

14:40 Overview of the XRTC Single-Event Test Results on the Xilinx 7-Series FPGAs - Gary Swift (Swift Engineering and Radiation Services, LLC)

15:25 Results of Heavy-Ion Broad and Micro Beam Testing of Flash-Based FPGAs - Adrian Evans (IROC Technologies)
15:55 Networking Coffee Break sponsored by Thales Communications & Security
Networking Coffee Break sponsored by Thales Communications & Security
15:55 - 16:25
Room: Newton 2
16:25
16:25 - 16:55
Room: Newton 2
Contributions

16:25 Single Event Upset Characterization of Commercial Grade SRAM and FLASH-based Field Programmable Gate Array Using Proton Irradiation - Tomáš Vaňát (Nuclear Physics Institute of the ASCR)
16:55
16:55 - 17:50
Room: Newton 2
Contributions

16:55 VHDL Best Practices and Design Principles for FPGA /ASIC - Florent Manni (CNES) Gabriel Liabeuf (CNES)

17:20 Introduction to the up-coming new ECSS Handbook on "Techniques for Radiation Effects Mitigation in ASICs and FPGAs" - Agustin Fernandez Leon (ESA)
17:50 Wrap up and Open discussion - David Dangla (CNES) David Merodio Codinachs (ESA)
Wrap up and Open discussion
- David Dangla (CNES)
- David Merodio Codinachs (ESA)
17:50 - 18:10
Room: Newton 2
Thursday 18 September 2014
08:50 SEFUW Intro - Opening Remarks - David Merodio Codinachs (ESA) David Dangla (CNES)
SEFUW Intro - Opening Remarks
- David Merodio Codinachs (ESA)
- David Dangla (CNES)
08:50 - 09:00
Room: Newton 2 Opening remarks by David Dangla (CNES) and David Merodio Codinachs (ESA)
09:00
09:00 - 10:00
Room: Newton 2
Contributions

09:00 Automated techniques for Building-in High Reliability and debugging your FPGA design - Frank McMillan (Synopsys)
10:00
10:00 - 10:45
Room: Newton 2
Contributions

10:00 EREMS Feedback about flight FPGA development - Rémi Sarrere (EREMS) Sandrine Zaouche (EREMS)

10:30 Algorithm implementation on ATF280 and CPUGEN board - Laurent Perraud (CNES)
10:45 Networking Coffee Break sponsored by Thales Communications & Security
Networking Coffee Break sponsored by Thales Communications & Security
10:45 - 11:10
Room: Newton 2
11:10
11:10 - 12:40
Room: Newton 2
Contributions

11:10 BRAM Radiation Sensor for a Self-Adaptive SEU Mitigation - Robért Glein (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU))

11:40 ESTEC experience for Flash-based FPGAs in Space: design and verification guidelines for critical applications - Gianluca Furano (ESA)

12:10 Static Design-Dependent SEE rates on SRAM-based FPGAs: a designer flow - David Merodio Codinachs (ESA)
12:40 Concluding remarks and closure - David Dangla (CNES) David Merodio Codinachs (ESA)
Concluding remarks and closure
- David Dangla (CNES)
- David Merodio Codinachs (ESA)
12:40 - 13:00
Room: Newton 2