TEC-ED & TEC-SW Final Presentation Days - December 2016

Speaker List

• Elena Alaña Salazar (GMV)
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    Verification of Computer-Controlled Systems

• Benjamin Bittner (Fondazione Bruno Kessler)
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    Enabling FDIR design through diagnosability and recoverability analysis

• Simon Bliudze (EPFL)
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    Catalogue for System and Software Properties - CSSP

• Victor Bos (SSF)
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    Catalogue for System and Software Properties - CatSY

• Marco Bozzano (Fondazione Bruno Kessler)
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    Consolidation of COMPASS tools

• Harold Bruintjes (RWTH Aachen University)
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    Consolidation of COMPASS tools

• Daniel Cederman (Cobham Gaisler AB)
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    Definition and Design of software components for LEON3FT Microcontroller and LEON-REX Instruction Set Architecture

• Martin Daněk (Daiteq s.r.o.)
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    Multi-threaded processor for space applications

• Brice Dellandrea (Thales Alenia Space - France)
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    SpaceWire Electrical Testing

• Alberto Ferrazzi (Terma)
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    Extensions and Validation of Virtual Platform for complex System-on-Chip and IP Cores Design for Space

• Kathleen Gerlo (ESA/ESTEC - Software Systems Division)
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    Registration

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    Registration

• Jérôme Hugues (ISAE SUPAERO)
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    TASTE Multicore

• Chris Jesshope
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    Multi-threaded processor for space applications

• Glenn Johnson (SciSys)
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    OBC Mass Memory (Solid State mass Memory Board/Module Integrated in OBC)

• Andreas Jung (ESA/ESTEC)
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    Improvement of the OSRA SCM Model Editor

• Panagiotis Katsaros (CERTH)
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    Schedulability Analysis Techniques and Tools for Cached and Multicore Processors

• Panagiotis Katsaros (AUTh)
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    Catalogue for System and Software Properties - CSSP

• Goulwen Le Fur (Obeo)
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    Improvement of the OSRA SCM Model Editor

• Richard Melvin (SciSys)
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    Deploying Plug and Play Avionics

• Pablo Muñoz (University of Alcalá)
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    Benchmarking Autonomous Robotics Controllers (NPI Activity)

• Claire Pagetti (ONERA)
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    TASTE Multicore

• Cristina Plettner (Airbus DS Bremen)
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    Ethernet PHY characterisation

• Marco Ruiz (SABCA)
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    CLP: Control Loop Processor, Architectural Design, Verification and FPGA prototypes

• Michael Ryan (O.C.E. Technology)
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    DMON and the AGGA 4

• Patrick Sandin (RUAG Space AB)
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    OBC Mass Memory (Solid State mass Memory Board/Module Integrated in OBC)

• Felix Siegle (Cobham Gaisler AB)
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    Space Fibre IP core

• Bertilla Sinka (ESTEC)
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    Registration

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    Registration

• Emil Vassev (LERO)
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    LLVM compiler for in flight SW development and validation process

• Dietmar Walter (DSI)
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    OBC Mass Memory (Solid State mass Memory Board/Module Integrated in OBC)