Name: TEC-ED & TEC-SW Final Presentation Days - May 2017
Start: 2017-05-08T09:00:00+02:00
End: 2017-05-09T17:10:00+02:00
Location: ESA/ESTEC

TEC-ED & TEC-SW Final Presentation Days - May 2017

from Monday, 8 May 2017 (09:00) to Tuesday, 9 May 2017 (17:10)

Monday, 8 May 2017

09:30 Registration + Coffee
Registration + Coffee
09:30 - 10:30
Room: Newton 2

10:30 Welcome & Introduction
Welcome & Introduction
10:30 - 10:40
Room: Newton 2
10:40 SHyLoC: CCSDS Lossless Compression IP-Cores for Space Applications - Lucana Santos (IUMA)
SHyLoC: CCSDS Lossless Compression IP-Cores for Space Applications
- Lucana Santos (IUMA)
10:40 - 11:20
Room: Newton 2
11:20 INSPECTOR – A supporting tool for AIT/AIV phase - Lukasz Kwiecinski (ITTI Ltd)
INSPECTOR – A supporting tool for AIT/AIV phase
- Lukasz Kwiecinski (ITTI Ltd)
11:20 - 12:00
Room: Newton 2
12:00 RTEMS Symmetric Multiprocessing Optimization and Improvement for LEON multi-core - Sebastian Huber (Embedded Brains) Matthias Goebel (Embedded Brains)
RTEMS Symmetric Multiprocessing Optimization and Improvement for LEON multi-core
- Sebastian Huber (Embedded Brains)
- Matthias Goebel (Embedded Brains)
12:00 - 12:40
Room: Newton 2
12:40 Lunch Break
Lunch Break
12:40 - 14:00
Room: Newton 2
14:00 Multicore Emulation on Virtualised Environment - Ruediger Gad (Terma GmbH)
Multicore Emulation on Virtualised Environment
- Ruediger Gad (Terma GmbH)
14:00 - 14:40
Room: Newton 2
14:40 Prototype SpaceWire RMAP Boot Software for Secondary Processor - Alberto Ferazzi (Terma GmbH) Mattias Holm (Terma GmbH)
Prototype SpaceWire RMAP Boot Software for Secondary Processor
- Alberto Ferazzi (Terma GmbH)
- Mattias Holm (Terma GmbH)
14:40 - 15:20
Room: Newton 2
15:20 SpaceWire Node Interface IP Core - Antonis Tavoularis (Teletel)
SpaceWire Node Interface IP Core
- Antonis Tavoularis (Teletel)
15:20 - 16:00
Room: Newton 2
16:00 Coffee Break
Coffee Break
16:00 - 16:30
Room: Newton 2
16:30 SPI Protocol Implementation for Space - Antonio Tramutola (TAS-I) Antonis Tavoularis (Teletel)
SPI Protocol Implementation for Space
- Antonio Tramutola (TAS-I)
- Antonis Tavoularis (Teletel)
16:30 - 17:10
Room: Newton 2
17:10 Cosmic Vision Technology Test Vehicle Design and Evaluation Activities - Daniel Gonzalez (Arquimea)
Cosmic Vision Technology Test Vehicle Design and Evaluation Activities
- Daniel Gonzalez (Arquimea)
17:10 - 17:50
Room: Newton 2
Tuesday, 9 May 2017

08:30 Registration
Registration
08:30 - 09:00
Room: Newton 2
09:00 Ethernet PHY Characterisation - Cristina Plettner (Airbus DS)
Ethernet PHY Characterisation
- Cristina Plettner (Airbus DS)
09:00 - 09:40
Room: Newton 2
09:40 FT-UNSHADES maintenance - Hipólito Guzmán Miranda (Univ. of Sevilla)
FT-UNSHADES maintenance
- Hipólito Guzmán Miranda (Univ. of Sevilla)
09:40 - 10:20
Room: Newton 2
10:20 SETA tool update: SETs in Flash-based FPGAs - Luca Sterpone (PdiTorino)
SETA tool update: SETs in Flash-based FPGAs
- Luca Sterpone (PdiTorino)
10:20 - 11:00
Room: Newton 2
11:00 Coffee Break
Coffee Break
11:00 - 11:30
Room: Newton 2
11:30 KIPSAT 2: Deep Sub-Micron C65SPACE - Thierry Scholastique (STMicroelectronics)
KIPSAT 2: Deep Sub-Micron C65SPACE
- Thierry Scholastique (STMicroelectronics)
11:30 - 12:10
Room: Newton 2
12:10 High Performance Data Processor (HPDP): Architecture and Back-end Flow - Constantin Papadas (ISD)
High Performance Data Processor (HPDP): Architecture and Back-end Flow
- Constantin Papadas (ISD)
12:10 - 12:50
Room: Newton 2
12:50 Lunch Break
Lunch Break
12:50 - 14:00
Room: Newton 2
14:00 Assessment of the Implementation of the EFL Time-Randomised Cache in the NGMP Architecture - Francisco Cazorla (BSC) Carles Hernandez (BSC)
Assessment of the Implementation of the EFL Time-Randomised Cache in the NGMP Architecture
- Francisco Cazorla (BSC)
- Carles Hernandez (BSC)
14:00 - 14:40
Room: Newton 2
14:40 Modular RTU - Javier Goyanes (CRISA)
Modular RTU
- Javier Goyanes (CRISA)
14:40 - 15:20
Room: Newton 2
15:20 Coffee Break
Coffee Break
15:20 - 15:50
Room: Newton 2
15:50 AUTOCOGEQ - Preparation for the Qualification of Auto-Code Generated from Simulink Models - Francesco Pace (GMV)
AUTOCOGEQ - Preparation for the Qualification of Auto-Code Generated from Simulink Models
- Francesco Pace (GMV)
15:50 - 16:30
Room: Newton 2
16:30 GRSRIO - Serial RapidIO Logical Layer IP Core Flexible DMA Engine for Serial RapidIO Endpoints - Stefano Di Mascio (Cobham Gaisler)
GRSRIO - Serial RapidIO Logical Layer IP Core Flexible DMA Engine for Serial RapidIO Endpoints
- Stefano Di Mascio (Cobham Gaisler)
16:30 - 17:10
Room: Newton 2