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TEC-ED & TEC-SW Final Presentation Days - May 2017

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Newton 2 (ESA/ESTEC)

Newton 2

ESA/ESTEC

Keplerlaan 1 2201 AZ Noordwijk The Netherlands
Kjeld Hjortnaes (ESA/ESTEC - Software Systems Division), Philippe Armbruster (ESA/Data Systems Division)
Description

The Software Systems Division (TEC-SW) and Data Systems Division (TEC-ED) Final Presentation Days are scheduled on Monday 8 May & Tuesday 9 May in conference room Newton 2 (ESA/ESTEC, The Netherlands)

All material presented at the workshop must, before submission, be cleared of any restrictions preventing it from being published on this web-site.

Presentations (zip file)
Participants
  • Adam Trcka
  • Alberto Ferrazzi
  • Alexandre Santos Mendes
  • Andreas Jung
  • Andrew Butterfield
  • Antonio Tramutola
  • Antonios Tavoularis
  • Arne Samuelsson
  • Athanasios Tsiodras
  • Bert-Johan Vollmuller
  • Carles Hernandez
  • Carlos Urbina Ortega
  • Christian M. Fuchs
  • Constantin Papadas
  • Cristina Plettner
  • Daniel González
  • Daniele Rolfo
  • David Sanchez de la Llana
  • Domenico Giunta
  • Eduardo Sanchez Suarez
  • Emmanuel Lesser
  • Eric Reinthal
  • Erik Wegkamp
  • Ernesto Pun
  • Fernando Aldea
  • Francesco Pace
  • Francisco J Cazorla
  • Francisco Javier Moreno Carrillo
  • giorgio magistrati
  • Harm-Jan de Graaf
  • Hipólito Guzman Miranda
  • Ingo Saenger
  • Javier Goyanes
  • Jean-Loup TERRAILLON
  • Jorge Peña
  • Josep Rosello
  • Konrad Nieradka
  • Krzysztof Samp
  • Luca Sterpone
  • Lucana Santos
  • Manrico Fedi Casas
  • Manuel Fernandez
  • Margarita Pereira
  • Mathilde Maury
  • Mattias Holm
  • Mike Hinchey
  • Milos Melicher
  • Nick Panagiotopoulos
  • Paul Muller
  • Peter Gorm Larsen
  • pierre HIRSCHAUER
  • Pieter van Duijn
  • Ralf Lange
  • Richard Wiest
  • Roberto Sarmiento
  • Ruediger Gad
  • Sebastian Huber
  • Stefano Di Mascio
  • Stefano Redi
  • Steven De Cuyper
  • Sven Rohrdanz
  • Thierry Scholastique
  • Tiago Hormigo
  • Łukasz Kwieciński
Support
  • Monday, 8 May
    • 09:30
      Registration + Coffee
    • 1
      Welcome & Introduction
    • 2
      SHyLoC: CCSDS Lossless Compression IP-Cores for Space Applications
      Speaker: Ms Lucana Santos (IUMA)
      Abstract
      Presentations
    • 3
      INSPECTOR – A supporting tool for AIT/AIV phase
      Speaker: Mr Lukasz Kwiecinski (ITTI Ltd)
      Abstract
      Presentations
    • 4
      RTEMS Symmetric Multiprocessing Optimization and Improvement for LEON multi-core
      Speakers: Mr Matthias Goebel (Embedded Brains), Mr Sebastian Huber (Embedded Brains)
      Abstract
      Presentation
    • 12:40
      Lunch Break
    • 5
      Multicore Emulation on Virtualised Environment
      Speaker: Mr Ruediger Gad (Terma GmbH)
      Abstract
      Presentation
    • 6
      Prototype SpaceWire RMAP Boot Software for Secondary Processor
      Speakers: Mr Alberto Ferazzi (Terma GmbH), Dr Mattias Holm (Terma GmbH)
      Abstract
      Presentation
    • 7
      SpaceWire Node Interface IP Core
      Speaker: Mr Antonis Tavoularis (Teletel)
      Abstract
      Presentation
    • 16:00
      Coffee Break
    • 8
      SPI Protocol Implementation for Space
      Speakers: Mr Antonio Tramutola (TAS-I), Mr Antonis Tavoularis (Teletel)
      Abstract
      Presentation
    • 9
      Cosmic Vision Technology Test Vehicle Design and Evaluation Activities
      Speaker: Mr Daniel Gonzalez (Arquimea)
      Abstract
      Presentations
  • Tuesday, 9 May
    • 08:30
      Registration
    • 10
      Ethernet PHY Characterisation
      Speaker: Dr Cristina Plettner (Airbus DS)
      Abstract
      Presentations
    • 11
      FT-UNSHADES maintenance
      Speaker: Dr Hipólito Guzmán Miranda (Univ. of Sevilla)
      Abstract
      Presentations
    • 12
      SETA tool update: SETs in Flash-based FPGAs
      Speaker: Prof. Luca Sterpone (PdiTorino)
      Abstract
      Presentations
    • 11:00
      Coffee Break
    • 13
      KIPSAT 2: Deep Sub-Micron C65SPACE
      Speaker: Mr Thierry Scholastique (STMicroelectronics)
      Abstract
      Presentations
    • 14
      High Performance Data Processor (HPDP): Architecture and Back-end Flow
      Speaker: Mr Constantin Papadas (ISD)
      Abstract
      Presentation
    • 12:50
      Lunch Break
    • 15
      Assessment of the Implementation of the EFL Time-Randomised Cache in the NGMP Architecture
      Speakers: Mr Carles Hernandez (BSC), Mr Francisco Cazorla (BSC)
      Abstract
      Presentation
    • 16
      Modular RTU
      Speaker: Mr Javier Goyanes (CRISA)
      Abstract
      Presentations
    • 15:20
      Coffee Break
    • 17
      AUTOCOGEQ - Preparation for the Qualification of Auto-Code Generated from Simulink Models
      Speaker: Mr Francesco Pace (GMV)
      Abstract
      Presentations
    • 18
      GRSRIO - Serial RapidIO Logical Layer IP Core Flexible DMA Engine for Serial RapidIO Endpoints
      Speaker: Mr Stefano Di Mascio (Cobham Gaisler)
      Abstract
      Presentations
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