FPD'17

D1P8 - ARTES AT - SiGe VCO Block - CoreHW (Finland), VTT (Finland)

14 Feb 2017, 17:00

30m

Newton 1 & 2 (ESA/ESTEC)

Speaker

Mr Sami Sipilä (CoreHW)

Description

In this activity, the main objective was to design a SiGe VCO block for the frequency range of 1.25 GHz – 3.3 GHz with very low phase noise requirement. Two VCOs were designed, fabricated and measured; one VCO utilizing cross-coupled PMOS transistors and other HBT transistors. VCOs exploit RHBD techniques, such as triple redundancy and voting in digital control. VCOs were irradiated in ESTEC Co-60 facility. Total Dose was 1.354 kGy with rate of 31.48 Gy/h. No significant deterioration in VCO performance was observed compared to pre-irradiation measurements. VCOPMOS, operating up to 3.5 GHz, achieved phase noise lower than -112 dBc/Hz @ 100 kHz within 1.25 GHz - 3.3 GHz. VCOBJT, operating from 0.7 GHz to 6.6 GHz, had phase noise of lower than -111 dBc/Hz @ 100 kHz at the 1.25 GHz - 3.3 GHz. Output power of VCOs is higher than 0 dBm and S22 < -10 dB. Both VCOs operate from 5 V with current consumption less than 120 mA.

Short Speaker Information

Sami Sipilä received the M. Sc. degree in telecommunications from Tampere University of Technology, Finland, in 1998. Between 1996-2000 he worked as a RF, Analog and Mixed-mode designer in VLSI Solution, Finland. From 2000 he worked in Tampere University of Technology as a researcher. During this time, he was also a principal lecturer in several RFIC-based courses such as Communications Circuits and Modules and RF-ASIC Design.
He joined CoreHW 2013, where he is presently Senior RF designer. His current tasks are focused on the research and designs of VCOs, LNAs and Power Amplifiers.
For the project of SiGe VCO block, he operated as a leader of the technical implementation.