Speaker
Mr
Mauro Caleno
(ESA/ESTEC - Software Systems Division)
Description
Activity: GSTP & Strategic Initiative Denmark
ESA TO: Mr. Mauro Caleno - Software Systems Division
The goal of the project “OBC Simulator Architectures and Interfaces to System Test Benches” is to define architectures and interfaces for simulators of on-board computers based on Leon 2 and Leon 3 System on Chips (SoC). The primary output of the activity is a PCIe FPGA Leon Emulation Board (LEB) together with a number of reusable VHDL and software simulation components to tailor the FPGA to a specific target SoC. The LEB executes the actual Leon VHDL code thus enabling hardware-in-the-loop (HIL) emulation of Leon SoC’s. The LEB designed for Linux workstations and is controlled via an API compatible with TSIM by Aeroflex-Gaisler. The activity also has two secondary goals: exploring whether a model of a spacewire IP Core written by hardware engineers in SystemC/TLM could be reused in an OBC simulator (HW/SW engineering); and exploiting the SOIS layered architecture to skip simulation of and abstract from the OBC HW/SW ICD in an OBC simulator.
This GSTP project started in March 2013 with Astrium SAS (France) and Terma AS (Denmark) and is currently under extension by CCN due to conclude with the Acceptance Review in September 2014. However the project has already achieved large part of its baseline goals, so its status is being presented at the FPD in May and at the DASIA.
The LEB is an evolution of the earlier project “Leon Software Validation Facility” presented at DASIA 2008. The LEB enables connecting software simulations to addresses in the I/O space, internal APB and AHB AMBA spaces, managing simulation time events as well as transmitting and receiving entire spacewire packets when a SpW IP Core is embedded in the FPGA. The transfer of entire spacewire packets and connecting simulations to the internal APB and AHB AMBA busses are new function that enable HIL simulation of SoCs. Whenever simulation events trigger (I/O, AMBA, time or packet), the clock signal to the Leon IP Core is suspended to keep time representativity for the on-board software (OBSW) while the simulations execute. The project produced 3 configurations of the LEB for the Atmel AT697, for a generic Leon3 configuration and for a Leon3 configuration inspired from the SCOC3 SoC by Astrium and which embeds the Spacewire IP Cores. The LEB is the core of the OBC simulator integrated in the EagleEye ATB in the ESTEC avionics Lab via SMP2 interfaces.
