Name: SEFUW: SpacE FPGA Users Workshop, 5th Edition
Start: 2020-03-17T09:15:00+01:00
End: 2020-03-19T17:00:00+01:00
Location: European Space Research and Technology Centre (ESTEC)

SEFUW: SpacE FPGA Users Workshop, 5th Edition

from Tuesday, March 17, 2020 (9:15 AM) to Thursday, March 19, 2020 (5:00 PM)

Monday, March 16, 2020
Tuesday, March 17, 2020

9:15 AM Registration and Networking Coffee Break
Registration and Networking Coffee Break
9:15 AM - 10:00 AM
Room: Newton 1 and 2
10:00 AM
10:00 AM - 11:40 AM
Room: Newton 1 and 2
Contributions

10:00 AM Challenges with New FPGA Technologies - Isaac Tejerina Bustillo (Airbus Defence & Space)

10:25 AM MPSOCS FOR RECONFIGURABLE MODULAR SPACECRAFT - Matthew Rowlings (Staff)

10:50 AM Development and FPGA Roadmap for LEON5FT and NOEL-V Processor Models - Martin Ronnback (Cobham Gaisler)

11:15 AM SpaceFibre and SpaceWire IP cores for radiation tolerant FPGAs - Chris McClements (STAR-Dundee) Steve Parkes (STAR-Dundee)
11:40 AM
11:40 AM - 1:00 PM
Room: Newton 1 and 2
Contributions

11:40 AM Getting Started with OSVVM, VHDL's #1 Verification Methodology - Jim Lewis (SynthWorks Design Inc.)

12:10 PM Using Static RTL Analysis to Accelerate Space FPGA Verification - adam adam taylor (Adiuvo Engineering & Training Ltd)

12:35 PM A UML Profile for VHDL FPGA Designs. - Harald Ottacher (Space Research Institute / Austrian Academy of Sciences)
1:00 PM Networking Luncheon
Networking Luncheon
1:00 PM - 2:00 PM
Room: ESTEC Canteen
2:00 PM
2:00 PM - 3:00 PM
Room: Newton 1 and 2
Contributions

2:00 PM Saving Power and System Cost with Microchip Radiation Tolerant FPGAs - Ken O'Neill (Microchip Technology)
3:00 PM
3:00 PM - 4:30 PM
Room: Newton 1 and 2
Contributions

3:00 PM Automation of achieving Functional Safety and Highly Reliable Design - Philipp Jacobsohn (Synopsys GmbH)

3:20 PM Harsher-than-space: Fault injection and user-based RHBD in the age of rad-tolerant and rad-hard devices - Hipólito Guzmán-Miranda (Universidad de Sevilla)

3:45 PM VeriPy: A Python Framework for the analysis and mitigation of soft-errors effects in SRAM-based FPGAs - Corrado De Sio (Politecnico di Torino)

4:00 PM Accurate Estimation of NXmap Circuit Performance and Reliability by Static Analysis and Simulation - Luca Sterpone (Politecnico di Torino)

4:15 PM New extensions for the LEON2FT IP core - Martin Danek (daiteq)
4:30 PM Networking Coffee Break
Networking Coffee Break
4:30 PM - 5:00 PM
Room: Newton 1 and 2

5:00 PM Demo Session/Exhibit and Welcome Reception
Demo Session/Exhibit and Welcome Reception
5:00 PM - 7:00 PM
Room: Wintergarden South
Wednesday, March 18, 2020

8:50 AM SEFUW Intro - Opening Remarks
SEFUW Intro - Opening Remarks
8:50 AM - 9:00 AM
Room: Newton 1 and 2
9:00 AM
9:00 AM - 10:30 AM
Room: Newton 1 and 2
Contributions

9:00 AM Webex session: Methods for Mission-Critical Survivability Analysis - Melanie Berg (Space R2 LLC)

9:50 AM Methodologies and tools to efficiently perform fault campaigns to measure functional safety - Joerg Richter (Group Director R&D, Verification Group)

10:10 AM Configuration Memory Scrubber for the Xilinx Zynq-7000 FPGA based on a 2D coding scheme - Mihalis Psarakis (University of Piraeus, Greece)
10:30 AM
10:30 AM - 11:20 AM
Room: Newton 1 and 2
Contributions

10:30 AM FPGA Based Reconfigurable On-Board Payload Processing for an Exploratory In-Orbit Verification of an E-Band (71-76 GHz) Satellite Link (EIVE) - Laura Manoliu (University of Stuttgart)

10:55 AM Use of Cyclone V SoC in OPS-SAT mission of ESA - Vasundhara Shiradhonkar
11:20 AM Networking Coffee Break
Networking Coffee Break
11:20 AM - 11:50 AM
Room: Newton 1 and 2
11:50 AM
11:50 AM - 1:00 PM
Room: Newton 1 and 2
Contributions

11:50 AM FPGA continuous integration - Florent MAnni (DC/TV/IN)

12:10 PM UVVM usage is exploding. A brief introduction and all the new stuff for this standardised VHDL verification methodology. - Espen Tallaksen (Bitvis)

12:40 PM Accelerating the Journey from C/C++ to Hardware - Pantelis Sarais (Silexica)
1:00 PM Networking Luncheon
Networking Luncheon
1:00 PM - 2:00 PM
Room: ESTEC Canteen
2:00 PM
2:00 PM - 3:00 PM
Room: Newton 1 and 2
Contributions

2:00 PM Xilinx’s Adaptive FPGAs for Space Applications - Minal Sawant (Xilinx Inc.)
3:00 PM
3:00 PM - 4:15 PM
Room: Newton 1 and 2
Contributions

3:00 PM Computer Vision Acceleration on NG-MEDIUM and NG-LARGE FPGAs for Rovers - George Lentaris (National Technical University of Athens, Greece)

3:25 PM Modulable architecture for image processing systems - Rubén Domingo Torrijos (GMV)

3:50 PM Performance Assessment of Onboard CCSDS Forward Error Correction on Space FPGAs - Nektarios Kranitis (Dept. of Informatics &amp; Telecommunications, National and Kapodistrian University of Athens)
4:15 PM Networking Coffee Break
Networking Coffee Break
4:15 PM - 4:45 PM
Room: Newton 1 and 2
4:45 PM
4:45 PM - 5:35 PM
Room: Newton 1 and 2
Contributions

4:45 PM RTG4 FPGA in ATHENA WFI - Markus Plattner (Max Planck Institute for extraterrestrial Physics)

5:10 PM The data processing unit for the PMI instrument aboard the Lagrange mission - Juan Pedro Cobos Carrascosa (Institute of Astrophysics of Andalusia)
5:35 PM Round Table
Round Table
5:35 PM - 6:30 PM
Room: Newton 1 and 2

7:30 PM SEFUW Dinner
SEFUW Dinner
7:30 PM - 9:30 PM
Thursday, March 19, 2020

8:50 AM SEFUW Intro - Opening Remarks
SEFUW Intro - Opening Remarks
8:50 AM - 9:00 AM
Room: Newton 1 and 2
9:00 AM
9:00 AM - 10:00 AM
Room: Newton 1 and 2
Contributions

9:00 AM NanoXplore NXmap-v3 features and updated NX products portfolio - JOEL LE MAUFF (NanoXplore)
10:00 AM
10:00 AM - 10:50 AM
Room: Newton 1 and 2
Contributions

10:00 AM Fault tolerance analysis of iterative processing data-paths - Alexandru Amaricai (University Politehnica Timisoara)

10:25 AM Radiation tolerant CAN controller for Xilinx FPGAs - Simon Voigt Nesbo (Western Norway University of Applied Sciences)
10:50 AM Networking Coffee Break
Networking Coffee Break
10:50 AM - 11:20 AM
Room: Newton 1 and 2
11:20 AM
11:20 AM - 1:00 PM
Room: Newton 1 and 2
Contributions

11:20 AM Xilinx Machine Learning Solutions and Design Considerations for Space Applications - Jason Vidmar (Xilinx Corp)

11:45 AM Image Recognition for Space Applications using Deep Learning on FPGAs & SoCs - Stephan van Beek (MathWorks)

12:10 PM FPGA implementation of Cloud Detection algorithm based on Convolutional Neural Network for Earth Observation applications On board - Giamarco Dinelli (University Of Pisa) Gionata Benelli (IngeniArs)

12:35 PM Intel’s Solution for Fast and Efficient Inference - Ruth Abra (Intel)
1:00 PM Networking Luncheon
Networking Luncheon
1:00 PM - 2:00 PM
Room: ESTEC Canteen
2:00 PM
2:00 PM - 2:15 PM
Room: Newton 1 and 2
Contributions

2:00 PM FUSIO RT update: First European Space Computer Core, Ready to use - Coralie Dang Feller (3DPLUS)
2:15 PM
2:15 PM - 2:35 PM
Room: Newton 1 and 2
Contributions

2:15 PM 3D PLUS CONFIGURATION MEMORY SOLUTIONS - Jeanne TONGBONG

2:25 PM High Performance Memories To Augment Space FPGA s - Helmut Puchner (Cypress Semiconductor)
2:50 PM
2:50 PM - 4:30 PM
Room: Newton 1 and 2
Contributions

2:50 PM First Design-In Experiences and Comparison of KU060, NG-ULTRA and RTPolarFire for On-Board Processing and AI - Rajan Bedi (Spacechips)

3:15 PM Flexible FPGA Architecture for Compact High-Performance PDHU and OBC Mass Memory - Gang Zhou (DSI Aerospace Technologie GmbH )

3:40 PM Xilinx Zynq Ultrascale+ MPSoC-based modular unit for rapid spacecraft hardware prototyping - Michael Walshe (Thales Alenia Space)

4:05 PM Designing a low-latency Fail-operational motor controller for space on industrial-grade FPGAs - Aloïs Wolff (Watt&Well)
4:30 PM Concluding remarks and closure
Concluding remarks and closure
4:30 PM - 5:00 PM
Room: Newton 1 and 2

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