SEFUW: SpacE FPGA Users Workshop, 5th Edition

Session

Design Flow

17 Mar 2020, 11:40

Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

3. Getting Started with OSVVM, VHDL's #1 Verification Methodology

Jim Lewis (SynthWorks Design Inc.)

17/03/2020, 11:40

Design Flow

Open Source VHDL Verification Methodology (OSVVM) is an advanced verification methodology and library that simplifies the creation of structured, transaction-based tests and test environments that are powerful enough for ASIC verification, yet simple enough for small FPGA verification.

OSVVM is implemented as two separate open source libraries: OSVVM Utility Library and OSVVM Verification...

6. Using Static RTL Analysis to Accelerate Space FPGA Verification

Mr adam adam taylor (Adiuvo Engineering & Training Ltd)

17/03/2020, 12:10

Design Flow

Developing FPGAs which work across reliably in flight requires considerable thought. Reinforcing this challenge is that 84% of commercial FPGA designs make it to production with a non trivial error (source mentor graphics / wilson group survey).

To reduce the risk of a fault making it to flight or being found very late in the program. There need to be a number of rules followed for best...

22. A UML Profile for VHDL FPGA Designs.

Mr Harald Ottacher (Space Research Institute / Austrian Academy of Sciences)

17/03/2020, 12:35

Design Flow

To perform the design of an FPGA project, several graphical representations of the later coded implementation of the FPGA function can be used.
The usage of hardware description languages for the implementation enables also design approaches and representations that are used for software designs, as a basis for the FPGA implementation, like the well defined Unified Modeling Language...

42. FPGA continuous integration

Florent MAnni (DC/TV/IN)

18/03/2020, 11:50

Design Flow

In the beginning of this year, CNES conducted a one month project with three Students from Enseeiht School. The purpose was to try and gather feedback about continuous integration of FPGA development. The use case was a RiscV ioptimized processor targetting NanoXplore Medium FPGA. The tools used for this presentation were: Git, Gitlab,Gitlab-Ci,Doxygen,Sonarqube-Rulechecker,Cocotb,Nxmap,Ghdl....

19. UVVM usage is exploding. A brief introduction and all the new stuff for this standardised VHDL verification methodology.

Mr Espen Tallaksen (Bitvis)

18/03/2020, 12:10

Design Flow

Verification is critical for an acceptable FPGA quality. Unfortunately, achieving a good FPGA quality is often very time consuming. However, with a good testbench architecture the workload could be reduced significantly. UVVM provides the best VHDL testbench architecture possible and also allows a unique reuse structure. Entry level UVVM is dead simple even for beginners, and for more advanced...

31. Accelerating the Journey from C/C++ to Hardware

Mr Pantelis Sarais (Silexica)

18/03/2020, 12:40

Design Flow

High-Level Synthesis (HLS) methodologies is proposed since around 15 years as a promising design methodology. Nevertheless, software engineers are still not able to get the maximum benefit from HLS due to the required knowledge about both parallelism and the specific FPGA hardware architecture. This presentation will explore the common design challenges engineers face when using HLS and how...