Speakers
Description
This project was established to improve the verification of space related FPGA functionality – in order to improve quality and reduce development time. The project is based on UVVM (Universal VHDL Verification Methodology) – as a VHDL verification methodology with standardised handling of verification components, high level commands, functionality extension, split transactions and interface synchronisation, - focusing on overview, maintainability, extensibility, debuggability and efficient reuse.
The target for this project was to improve UVVM further to handle space related FPGA projects even better. The main functionalities to be added were Constrained Random, Functional Coverage and Test Regression support. All of this was totally new functionality, some of which was significant extensions on previous similar basic functionality. All this required functionality has been implemented and is delivered to ESA.
The Advanced Randomisation and Functional Coverage functionalities have already been published on Github, whereas the remaining functionality will be released over the next couple of months - after the already held successful final review, the external feedback and the internal re-review (after maturing and feedback) in both Inventas and EmLogic.
The result of the project has been very important and useful extensions on the UVVM verification system. New published functionality has already been used by lots of designers, and quite a few more designers will start using the functionality for their next project.
UVVM is now a great VHDL verification methodology for both FPGA and ASIC development and is in fact the world-wide most used VHDL verification methodology. Nevertheless, there is still room for important improvements that are under consideration.
