In recent years, we have witnessed a continuous reduction in technology nodes, accompanied by the ever-expanding resources within these devices. Concurrently, system architects are striving to implement in them more intricate solutions, while technology roadmaps demand faster time-to-market. As you can imagine, these factors pose formidable challenges to the industry's latest developments. How...
This presentation provides an overview of the use of high-level design and synthesis tools in recent FPGA-based design projects carried out in the logic design department of Airbus D&S Ottobrunn. This includes insights from the work with state-of-the-art tools like the MATLAB HDL Coder and Vitis HLS as they were gained when investigating application scenarios from domains like radar signal...
Nowadays, the continuous increase of the FPGAs complexity requires the adoption of new tools and flows to speed up the design from the modelling phase to the HW prototype. In this presentation, the design flow from high level specifications to the HW validation is proposed, focusing on the use of MATLAB/SIMULINK tools and automatic code generation with SIMULINK HDL-Coder.
We cannot develop as we have previously done with larger devices, tighter timescales and more functionality demanded. This presentation will introduce a flow which enables model-based design for FPGA, using SYSML the architecture, connectivity, registers and networks can be defined and auto generated to HDL. Enabling the model to be the master, this flow is designed to work with high level...
Real-time, dependable systems have become increasingly popular and frequent in today's digital disruption era. However, traditional verification and validation processes have proven to be inefficient and unsuitable due to their rigidness. These systems require adaptability during design time, leading to longer development cycles and life cycles with consecutive security updates and...
