17th ESA Workshop on Avionics, Data, Control and Software Systems ~ ADCSS2023

Session

Data Handling

14 Nov 2023, 09:00

Newton Conference Area (ESA/ESTEC)

16. Welcome & Introduction

14/11/2023, 09:00

11. What's next? Beyond HDLs in space FPGA development

Alberto Urbon (Telespazio for ESA)

14/11/2023, 09:10

In recent years, we have witnessed a continuous reduction in technology nodes, accompanied by the ever-expanding resources within these devices. Concurrently, system architects are striving to implement in them more intricate solutions, while technology roadmaps demand faster time-to-market. As you can imagine, these factors pose formidable challenges to the industry's latest developments. How...

39. Applied high-level design & synthesis: A case study of recent FPGA-based design projects from the space industry

Patrick Gest (Airbus DS - Germany)

14/11/2023, 09:30

This presentation provides an overview of the use of high-level design and synthesis tools in recent FPGA-based design projects carried out in the logic design department of Airbus D&S Ottobrunn. This includes insights from the work with state-of-the-art tools like the MATLAB HDL Coder and Vitis HLS as they were gained when investigating application scenarios from domains like radar signal...

40. FPGA Design and HDL Auto-Coding Using Model Based Flow

Roberto Romanato (Thales Alenia Space - Italy)

14/11/2023, 10:00

Nowadays, the continuous increase of the FPGAs complexity requires the adoption of new tools and flows to speed up the design from the modelling phase to the HW prototype. In this presentation, the design flow from high level specifications to the HW validation is proposed, focusing on the use of MATLAB/SIMULINK tools and automatic code generation with SIMULINK HDL-Coder.

41. FPGA Architect & Model Based Engineering

Adam Taylor (Adiuvo Engineering and Training Ltd.)

14/11/2023, 10:30

We cannot develop as we have previously done with larger devices, tighter timescales and more functionality demanded. This presentation will introduce a flow which enables model-based design for FPGA, using SYSML the architecture, connectivity, registers and networks can be defined and auto generated to HDL. Enabling the model to be the master, this flow is designed to work with high level...

42. Observation of real-time dependable systems

André Pedro (VORTEC-CoLab)

14/11/2023, 11:30

Real-time, dependable systems have become increasingly popular and frequent in today's digital disruption era. However, traditional verification and validation processes have proven to be inefficient and unsuitable due to their rigidness. These systems require adaptability during design time, leading to longer development cycles and life cycles with consecutive security updates and...

43. The METASAT FPGA Prototype: A High-Performance Multicore, AI SIMD and GPU RISC-V Platform for On-board Data Processing

Leonidas Kosmidis (BSC)

14/11/2023, 12:00

The METASAT Horizon Europe project, funded by the European Commission and started in January 2023, will enable model-based design methodologies in order to manage the complexity of upcoming parallel hardware and software for on-board data processing. As a representative, qualifiable and mixed criticality high performance platform for on-board processing, METASAT designs a multicore platform...

44. The PLATO On-board data-processing System – A Comprehensive Overview

Claas Ziemke (DLR)

14/11/2023, 12:30

The scientific goals of the PLATO mission are to search for planetary transits across a large number of stars. In this presentation we describe its on-board data processing architecture, including the 26 cameras and 14 data-processing units, the on-board data acquisition, processing and storage and the lessons learnt so far in implementing this system. In the case of PLATO, only the...

14. Autocoding FPGA firmware

13. High Level Synthesis via Xilinx Vitis y Model Based Design + HLS

12. Hiside Space Fiber based high speed network demonstrator

15. TBC