Speaker
Description
In space applications, SRAM-based FPGA devices are vulnerable to radiation-induced soft errors such as single event upsets (SEUs) and multiple bit upsets (MBUs), which can lead to system malfunctions. We have developed an experimental setup to perform fault injection campaigns in the configuration memory using the AMD Soft Error Mitigation (SEM) IP Core, emulating SEUs and MBUs in commercial off-the-shelf (COTS) SRAM-based FPGA devices. A key feature of our setup is the extraction of critical bits, which accelerates the fault injection process by focusing only on flipping the bits that could affect the design's operation. The setup includes a Python-based graphical user interface (GUI) that automates the generation of FPGA frame addresses for these critical bits and manages the fault injection campaign. It also generates real-time reliability reports. The source code for the Python GUI and VHDL example designs will be available in a public GitHub repository. In the workshop, we will demonstrate the procedure for measuring the reliability of both unprotected and protected designs, offering an alternative to radiation tests in accelerators. This work contributes to the reliable use of COTS FPGA devices in space applications.
Affiliation of author(s)
Universidad Rey Juan Carlos
| Track | Fault Tolerance Methodologies and Tools |
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