Speaker
Description
The Comet Interceptor mission, part of ESA’s F-class portfolio, aims to visit a long-period comet, originating from the Oort Cloud and entering the Solar System for the first time. The mission consists of three spacecraft—main spacecraft A and two ‘sub-spacecraft,’ B1 and B2. Spacecraft B2 is equipped with the Optical Periscopic Imager for Comets (OPIC), developed by the University of Tartu, to capture images of the comet nucleus and its environment during the flyby.
Given the mission’s brief proximity to the target and the risk of spacecraft damage from dust impacts, OPIC must operate autonomously to prioritize and transmit images of the comet nucleus during a critical moment of the flyby. Central to this functionality is the IMPRIO IP core, developed by Bitlake Technologies, which autonomously identifies the comet nucleus and extracts regions of interest (ROIs) for prioritization.
The IMPRIO IP core is required to process 2048 x 2048, 12-bit images at a minimum throughput of 6 frames per second (fps), addressing challenges such as the comet nucleus unknown shape, size, and unpredictable visual features. Its integration into the ProASIC3L FPGA—already constrained by the OPIC camera head’s image readout functionality—demanded a resource-efficient design without hardware-level DSP support.
To meet these constraints, a multiscale Laplacian of Gaussian blob detection algorithm was selected for its noise resilience, robustness to damaged pixels, and suitability for optimized FPGA implementation. The multiscale approach further enhances target centroid detection, adapting to variations in the nucleus size during the flyby.
The resulting IMPRIO IP core is integrated in the OPIC camera head (3D Plus 3DCM734-1-SS). It achieves ~7.1 fps, exceeding performance requirements while efficiently utilizing the FPGA’s available logic resources and maintaining the timing closure required for OPIC camera operation.
In this work, we will detail the design methodology, FPGA-specific optimizations, and performance validation of the IMPRIO IP core. Additionally, we will share insights and lessons learned from implementing image processing application on the resource-constrained platform
Affiliation of author(s)
Bitlake Technologies SIA
| Track | Industrial experience |
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