Speaker
Description
Higher-level methodologies, such as model-based design, enable the faster development of complex hardware-software FPGA designs while maintaining a reasonable quality of results compared to lower-level approaches.
In this presentation, we introduce the SpaceStudio virtual platform, which includes a specialized space toolkit to complement its ecosystem. This toolkit integrates the RTEMS real-time operating system (RTOS), Siemens Catapult HLS, and Precision Hi-Rel (High Reliability), a specialized variant of Siemens' Precision tool designed for critical applications requiring high reliability.
We propose a methodology for accelerating the development of fault-tolerant systems on Zynq Ultrascale+ MPSoC targets by leveraging high-level synthesis and fault-tolerant hardware synthesis tools.
The design is modeled as a network of modules, which can be mapped to software tasks or hardware accelerators on the FPGA. The module instances exchange data and control information through abstract communication channels, such as queues and registers. This approach enables the automated generation of the required structures based on the module's target.
This modular architecture facilitates a faster architecture exploration phase, as modules can be easily moved between hardware and software, and benchmarked both in simulation and on a more timing-accurate prototype using hardware execution time probes.
The methodology also incorporates a virtual platform that provides hardware-software co-simulation using SystemC and QEMU for Cortex-A53 and Cortex-R5 processors, significantly accelerating the functional verification of designs. By combining efficient software simulation and transaction-level modeling of hardware, this platform enables the simulation of complex designs that would otherwise require hours to simulate at the register-transfer level.
A key benefit for embedded software developers is the ability to develop and validate RTEMS drivers early in the project without requiring physical access to the FPGA board.
On the implementation side, Siemens' Catapult HLS enables the rapid hardware implementation of accelerators for computationally intensive algorithm modules, significantly reducing the effort needed to translate algorithms into register-transfer level (RTL) languages. Precision Hi-Rel efficiently synthesizes hardware code generated by Catapult, while providing built-in redundancy mechanisms, such as triple modular redundancy (TMR), to enhance fault tolerance. These fault-tolerance mechanisms are handled transparently, allowing systems to achieve higher reliability without additional development time.
The methodology will be demonstrated with an implementation of a corner-detection algorithm, a widely used component in Vision-Based Navigation to improve spacecraft position estimation and enable processes like landing and space rendezvous. This use case involves detecting key features in images, a computationally intensive task critical for navigation and mapping in space missions. The corner-detection algorithm benefits from the proposed fault-tolerance mechanisms, ensuring reliable performance despite hardware faults or unexpected conditions. The targeted platform is the ZCU102 board from the Zynq Ultrascale+ family, equipped with four ARM CPUs and FPGA fabric.
This work is one of the results of two NAVISP projects: Agnostic Hardware/Software Codesign Framework for GNSS Software Receiver (2019–2021) and HW/SW Codesign Environment (2022–2024).
Affiliation of author(s)
Space Codesign Systems
4388 Rue Saint-Denis Suite 200 #705
Montreal, Quebec
H2J 2L1 Canada
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