25–27 Mar 2025
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
Draft Agenda published

Security Module with HW-accelerated Post-Quantum Cryptography and TRNG for Reconfigurable Payload System-On-Chips in Space

26 Mar 2025, 12:10
25m
Einstein (European Space Research & Technology Centre)

Einstein

European Space Research & Technology Centre

Postbus 299 2200 AG Noordwijk (The Netherlands)
Oral presentation Artificial Intelligence/Machine Learning Artificial Intelligence/Machine Learning

Speaker

Mr Daniel Fortun (GMV GmbH)

Description

The space ecosystem is rapidly evolving, driven by the New Space paradigm, which emphasizes the use of commercial off-the-shelf (COTS) components and more powerful, reconfigurable payloads. This shift enables missions to dynamically adapt and enhance their capabilities in orbit. However, reconfigurable architectures based on SRAM-based FPGAs introduce security challenges, particularly regarding secure updates and protection against attacks. To address this, GMV is developing an embedded FPGA IP to serve as root of trust for reconfigurable payload controllers that is first being integrated on Alén Space’s TREVO SDR which uses Zynq Ultrascale+ with SRAM-based FPGA.

This implementation integrates post-quantum cryptography (PQC) with a focus on Kyber-512, ensuring secure key exchange resistant to quantum attacks. Additionally, a True Random Number Generator (TRNG) leveraging FPGA jitter physical source of randomness to enhance cryptographic robustness. The RoT is embedded in an immutable FPGA partition, while the remaining FPGA fabric remains reconfigurable for mission-specific processing. Initially, a hybrid HW/SW co-development approach was adopted, where PQC operations were partially implemented in software and accelerated in FPGA. Subsequently, a full FPGA-only solution was developed to enhance security by isolating cryptographic functions entirely within hardware.

The system further supports a Trusted Execution Environment (TEE), enabling secure enclave-based execution of sensitive operations while maintaining flexibility for payload reconfiguration. This architecture ensures a secure and scalable foundation for in-orbit reconfigurability, addressing the evolving needs of modern space missions while maintaining robust cryptographic security.

Affiliation of author(s)

GMV GmbH, GMV Innovating Solutions S.R.L., GMV Aerospace and Defence S.A.U.

Track FPGAs: High Performance

Primary authors

Mr Daniel Fortun (GMV GmbH) David Gonzalez-Arjona (GMV Aerospace and Defence)

Co-authors

Dr Arturo Pérez García (GMV Aerospace & Defence SAU) Mr Claudia Menendez (GMV Aerospace & Defence SAU) Mr Javier Fernandez-Gamo (GMV Aerospace & Defence SAU) Mr Marius Orza (GMV Innovating Solutions S.R.L.) Mr Martin Barez (GMV GmbH)

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