Speaker
Description
Firmware design represents one of the major sources of project delays in the LHC experiment upgrades. In the past, legacy electronic systems were ready to be used immediately after installation. However, recent experiences have demonstrated that it can take years until the firmware design is finished and the installed hardware is ready to be used. Higher abstraction design flows, such as high-level synthesis (HLS), reduce design cycles by enabling the designers to focus on the required functionality instead of hardware-specific details. This relieves the designer from specifying, for example, clock networks, reset trees, register transfers, and signal interfaces. Instead, they are automatically implemented using new synthesis steps in the HLS design flow such as register-transfer scheduling and enhanced resource allocation.
HLS is currently being used to design a new architecture for the ATLAS Liquid Argon Calorimeter trigger processor firmware. This system processes data from ~34k SuperCells obtained by summing the signals from physical calorimeter cells, using 120 large high-end FPGAs and ~5000 optical fibers routed from the experiment cavern to the computing room. The upgraded firmware aims to simplify firmware maintenance by unifying the data processing into a single clock domain instead of three, exploring more functionality in parallel instead of time-division multiplexing logic, and making it easier for non-firmware experts to contribute to the development thanks to the several automatic implementation steps available in the HLS design flow.
This work will cover the current status of the firmware upgrade of two modules that implement a highly flexible detector data interconnectivity using sparse-switch matrices and several steps of data aggregation and encoding used to generate the required output for the low-level trigger system. We will present our multi-stage functional simulation design flow that addresses increased levels of complexity in each of the stages for reduced simulation time and faster design cycles. We will also present in-system and laboratory validation tests followed by preliminary test results from the production system in the ATLAS cavern.
Affiliation of author(s)
CERN
| Track | High Level Synthesis and Model Based Design |
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