SEFUW: SpacE FPGA Users Workshop, 6th Edition

Session

Fault Tolerance Methodologies and Tools

25 Mar 2025, 10:15

Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

16. 3D+ - MNEMOSYNE: Radiation Tolerant Boot Memory

Mr Jerome SALLES

25/03/2025, 10:15

Fault Tolerance Methodologies and Tools

Oral presentation

SRAM-based FPGAs today need high-density configuration memories that are radiation-hardened for space applications. The MNEMOSYNE project aimed to design a radiation-hardened ASIC memory for boot and configuration.
I. RAD-HARD DESIGN:
IMEC designed the analog blocks (LDO, PMU, OSC, IVref, voltage monitors, etc …) using the RH DARE22 platform.
The digital design was done by 3D PLUS, while...

73. Space R3 - Differentiating Test Methods for Complex Components: Achieving the Ultimate Test-as-You-Fly

Mrs Melanie Berg (CEO Space R3 LLC)

25/03/2025, 10:40

Fault Tolerance Methodologies and Tools

Oral presentation

To be updated

27. Star Dundee - Evaluating AMD Versal FPGAs and SpaceFibre Under Heavy-Ion Radiation

Albert Ferrer (Star Dundee)

26/03/2025, 11:45

Fault Tolerance Methodologies and Tools

Oral presentation

The AMD Versal radiation-tolerant FPGA family represents a cutting-edge platform for high-performance applications. Versal offers unparalleled capabilities on space-qualified devices, featuring integrated GTY transceivers that support lane speeds of up to 25 Gbit/s. These attributes make them ideal for implementing advanced spacecraft communication protocols such as SpaceFibre (SpFi)....

45. Politecnico di Torino - Fast SEU Detection and Recovery in FPGA-Based AI Accelerators

Eleonora Vacca (Politecnico di Torino)

26/03/2025, 12:10

Fault Tolerance Methodologies and Tools

Oral presentation

The increasing complexity of deep learning models has created a demand for high-performance computing platforms that can efficiently execute inference tasks. FPGA's flexibility made them an appealing choice for accelerating such tasks. Recently, we also witnessed a growing interest in RISC-V-based solutions combined with dedicated AI accelerators to enhance computational capabilities. While...

69. ONERA/IES - ResNet50-based testbench development for the SEE evaluation of the AMD Versal SoC AIEngines

Salma Achaq (ONERA/IES)

26/03/2025, 12:35

Fault Tolerance Methodologies and Tools

Oral presentation

Hardware acceleration for an edge-AI application utilizing a convolutional neural network (CNN) typically involves distributing intensive computational tasks, such as matrix convolutions or multiplications, across multiple cores running in parallel. This can be achieved using a static GPU-like (Graphical Processing Unit) architecture or a configurable array of cores like the one available in...