16/09/2014, 09:30
Mr
David Dangla
(CNES), Mr
David Merodio Codinachs
(ESA)
16/09/2014, 10:00
Welcome by David Dangla (CNES) and David Merodio Codinachs (ESA)
Mrs
Valerie Briot
(ATMEL)
16/09/2014, 10:15
ATMEL has proven the principle of the RHBD FPGA after its first experiences on the AT40 and ATF280 devices .
Thanks to the use of RHBD FPGA, users do not have to take into account any mitigation techniques, SEE is guaranteed by design. And, thanks to the use of SRAM-based FPGA, users can perform unlimited reprogramming.
ATMEL is currently introducing new device and Multi Chip Modules...
Mr
Yohann Bricard
(ATMEL Nantes SAS)
16/09/2014, 11:05
ATMEL has been working for 1 year to improve the overall quality of the tools. A new team has been created to implement new quality standards, provide new features and Enhance Mentor Precision tool integration. It includes the management of pre-placed/routed IPs.
Prof.
Luca Sterpone
(Politecnico di Torino)
16/09/2014, 11:30
Single Event Upsets on SRAM-based FPGAs is a hot topic for more than a decade. After different investigations have been performed, a first algorithm for the prediction of SEU error probability on circuits on SRAM-based FPGAs is presented and analyzed by software prediction and fault injection analysis. Experimental results and comparison with other methods such as Xilinx Essential Bits report...
Dr
Hipolito Guzman Miranda
(Universidad de Sevilla), Dr
Miguel A. Aguirre
(Universidad de Sevilla)
16/09/2014, 12:00
Fault injection over an integrated circuit is a procedure that mimics the consequences of Single Event Effects within radiation environments, and checks, when they are transformed into faults, how are they managed by the circuit logic. During the normal flight time of the integrated circuit, radiation is one of the most relevant source of anomalies of the circuit functional behavior. Impacts...
Prof.
Luca Sterpone
(Politecnico di Torino)
16/09/2014, 12:30
Transient Pulse broadening is a realistic phenomena induced by high-energy
particles in deep-submicron technology. Electrical filtering has been demonstrated to be an effective solution to reduce the overall SET broadening effect. In this presentation an approach based on the Place and Route algorithm is presented and commented with a realistic application to Flash-based FPGAs.
Dr
George Lentaris
(National Technical University of Athens, Greece)
16/09/2014, 14:00
Future planetary exploration will rely on autonomous space rovers with increased moving speed and highly accurate visual odometry algorithms. ESA estimates that the 2020+ Mars missions will involve stereo cameras on robots moving at 6cm/s and calculating high definition depth maps in less than 20sec. Moreover, the error of these processes shall be less than 2m when traveling 100m paths and...
Mr
Dario Cozzi
(Bielefeld University)
16/09/2014, 14:30
Reconfigurable hardware is gaining a steadily growing interest in the domain of space applications. The ability to reconfigure the information processing infrastructure at runtime together with the high computational power of today’s FPGA architectures at relatively low power makes these devices interesting candidates for data processing in space applications. Partial dynamic reconfiguration...
Mr
Tobias Lange
(IDA, TU Braunschweig)
16/09/2014, 15:00
More than one and a half decade ago, the Data Processing Unit (DPU) of the Rosetta Orbiter Spectrometer for Ion and Neutral Analysis (ROSINA) instrument was developed at IDA using a processor system and 6 Actel RT14100A devices, providing a total capacity of only about 8k logic modules with fixed functionality. Nowadays, the DPU for the Polarimetric and Helioseismic Imager (PHI) instrument on...
Mr
David Dangla
(CNES), Mr
David Merodio Codinachs
(ESA)
17/09/2014, 08:50
Opening remarks by David Dangla (CNES) and David Merodio Codinachs (ESA)
Mr
Ken O'Neill
(Microsemi)
17/09/2014, 09:00
This presentation will provide an overview of key enabling technologies addressing the increasing demands for reduced size, weight and power (SWAP) and enhanced signal processing throughput in next generation space systems, without sacrificing reliability. RTG4 is Microsemi’s next generation FPGA family for radiation environments using a 65nm low-power flash process, which is immune to changes...
Mr
Daniel Elftmann
(Xilinx)
17/09/2014, 10:00
Xilinx has been producing Space grade Field Programmable Gate Array (FPGA) with flip chip ceramic column grid array packages since 2008 with its Virtex-4 FPGA family, adding Virtex-5 in 2011. This type of package is not well understood by the space community, and the JEDEC JC-13 participants and DLA-LM spent the past several years to develop the class Y Non-Hermetic Ceramic Packaging and...
Mr
Ottmar Ried
(Airbus DS GmbH)
17/09/2014, 11:10
In Airbus DS there is an extensive usage of Microsemi RTAX devices. Recently also the RTAX4000 FPGA has been introduced for a new project. The complexity of these type of devices have increased two fold:
- number of gate capacity, meaning higher complexity of the function
- number of pins, meaning higher complexity for assembly or repair
As a consequence potential late modifications, e.g....
Mr
Gregory Grimonet
(Thales Alenia Space)
17/09/2014, 11:40
Thales Alenia Space uses for several years FPGAs from various vendors which are chosen depending on their size, their performances and the application using it. This presentation will show the FPGAs used in TAS and how they are chosen. Moreover a concrete example will be developed.
Mr
Christophe Pourrier
(SODERN)
17/09/2014, 12:10
SODERN has recently used two different FPGA for earth observation missions. One ATMEL AT40K is embedded in the BSA sub-assembly of ATLID instrument for the EarthCARE satellite. It carries the whole digital functions that drive a 2-axis pointing mechanism. Commands and telemetries are transmitted through one serial link on request of the host processor. One MICROSEMI PROASIC3 is embedded in the...
Monica Alderighi
(INAF, Italy)
17/09/2014, 12:40
The talk illustrates the main features of two ESA projects that are currently on-going at INAF: FLIPPER 2 and Hi-Rel COTS based Computers for on board systems.
FLIPPER 2 represents the second release of the fault injection system for Xilinx SRAM-based FPGAs, developed by INAF. With respect to the previous release, it includes a DUT board specifically designed for Virtex 4 devices, and...
Dr
Giovanni Beltrame
(Polytechnique Montreal)
17/09/2014, 14:10
Particle and ionizing radiation can alter and severely disrupt the normal behavior of electronics, and lead to their premature failure. For this reason, computing systems for space applications have to be designed using methodologies to mitigate such issues. Field Programmable Gate Arrays (FPGAs) provided with reconfiguration capabilities can facilitate the implementation of fault-mitigation...
Mr
Gary Swift
(Swift Engineering and Radiation Services, LLC)
17/09/2014, 14:40
Since September 2013, the Xilinx Radiation Test Consortium collectively and individual members have been subjecting the Kintex-7, Artix-7, and Zynq devices to particle beam testing. Basic upset characteristics of configuration and block RAM and user flip-flops have been measured and clusters of upsets were observed.
Additionally, an unusual latchup-like, but non-destructive phenomenon of...
Mr
Adrian Evans
(IROC Technologies)
17/09/2014, 15:25
The first part of the presentation consists of an in-depth study of single event transients (SETs) in MicroSemi ProASIC3L FPGAs. The devices were tested at the Heavy-ion Irradiation Facility (HIF) at Louvain-La-Neuve, Belgium. Several combinatorial VersaTile configurations were studied in order to evaluate the effect of logic function and input state on SET sensitivity. The effect of...
Tomáš Vaňát
(Nuclear Physics Institute of the ASCR)
17/09/2014, 16:25
ALICE experiment at LHC collider in CERN laboratory in Geneva is preparing the upgrade of inner tracking system based on ~25 . 10^9 silicon pixel sensors with envisaged number of data links reaching 1000. Due to expected large number of FPGAs, only commercial grade FPGA can be considered. FPGA should have the reliable performance up to the expected lifetime total ionization dose of 10...
Mr
Florent Manni
(CNES), Mr
Gabriel Liabeuf
(CNES)
17/09/2014, 16:55
FPGA (and/or ASIC) are becoming the key element in the Electronic equipment.
Nowadays, the possibilities and the resources offered by these components allow to develop more and more complex systems. To cope with such technical challenges, designers have developed methodologies and rules specific to VHDL to reduce risk of failure. But, most of the time, those methodologies and knowledge are...
Mr
Agustin Fernandez Leon
(ESA)
17/09/2014, 17:20
After the completion in 2012 of the first draft of the ECSS–Q-HB-60-02 handbook through an ESA contract with TIMA(F), an ECSS Working Group of space IC experts was created in 2013 to revise and improve the contents of this document. The WG is working in order to release a final draft in March 2015 for ECSS public review.
Then, after receiving and implementing the final suggestions, it should...
Mr
David Dangla
(CNES), Mr
David Merodio Codinachs
(ESA)
17/09/2014, 17:50
Mr
David Dangla
(CNES), Mr
David Merodio Codinachs
(ESA)
18/09/2014, 08:50
Opening remarks by David Dangla (CNES) and David Merodio Codinachs (ESA)
Mr
Frank McMillan
(Synopsys)
18/09/2014, 09:00
There is a need for electronic systems to operate with high-reliability and high-availability in the face of radiation-induced “soft errors”. The need for high-reliability and high-availability electronic systems has now expanded to include many applications including communications infrastructure, industrial automation, control and medical devices but these soft errors are still of...
Mr
Rémi Sarrere
(EREMS), Ms
Sandrine Zaouche
(EREMS)
18/09/2014, 10:00
EREMS designs FPGAs according to a development flow which contains the following steps: final target selection, prototypes realisations, VHDL design including synthesis, place and route, performance analysis and finally component programming. The presentation outlines EREMS FPGA feedback based on space projects examples like CARMEN, PVL, TARANIS and CPUGEN. These missions are interesting to...
Mr
Robért Glein
(Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU))
18/09/2014, 11:10
In order to design a reliable FPGA system as a satellite On-Board Processor, firmware designers have to take Single Event Effects into account. Mitigation schemes (Triple Modular Redundancy, Algorithm-Based Fault Tolerance, …) ease the consequences of this effects. The main disadvantages of these mitigation schemes in FPGAs are resource overhead and additional path delay, depended on the type...
Mr
David Merodio Codinachs
(ESA)
18/09/2014, 12:10
The use of SRAM-based FPGAs in space equipment is growing. Their radiation-hardness needs to be assessed for the final application (i.e. design) that is implemented in the FPGA device.
The talk proposes an approach for FPGA designers to predict the SEE rates during the design activities. The first step addresses the computation of the static SEE rates of each architectural block of the FPGA...
Mr
David Dangla
(CNES), Mr
David Merodio Codinachs
(ESA)
18/09/2014, 12:40
