16–18 Sept 2014
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
Note: all available presentations have been posted on the website

Dynamically Reconfigurable Hardware for Resource Efficiency and Fault Tolerance in Space Applications

16 Sept 2014, 14:30
30m
Newton 2 (European Space Research and Technology Centre (ESTEC))

Newton 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands

Speaker

Mr Dario Cozzi (Bielefeld University)

Description

Reconfigurable hardware is gaining a steadily growing interest in the domain of space applications. The ability to reconfigure the information processing infrastructure at runtime together with the high computational power of today’s FPGA architectures at relatively low power makes these devices interesting candidates for data processing in space applications. Partial dynamic reconfiguration of FPGAs enables maximum flexibility and can be utilized for performance increase, for improving energy efficiency, and for enhanced fault tolerance. The DRPM platform (Dynamically Reconfigurable Processing Module) was developed as a highly scalable prototyping environment for satellite payload processing systems, combining dynamically reconfigurable FPGAs with the required interfaces such as SpaceWire, MIL-STD-1553B, and SpaceFibre. Partial reconfiguration of the FPGA area is supported by a dedicated hardware IP core, enabling maximum reconfiguration speed. Additionally, the IP core realizes blind and readback scrubbing with scrub rates that can be adapted individually for different parts of the design. The presentation will recap the architecture of the DRPM as well as interface and processing performance achievable using the DRPM platform for different applications with a special focus on the integrated SpaceFibre interfaces. Furthermore, the presentation will give details on the development of a tool flow for detection and correction of permanent faults in FPGAs during a space mission. Once faults have been detected and located, the flow generates fine-grained patch hard macros that are used to mask out the discovered faulty resources, allowing partially faulty regions of the FPGA to be available for further use. In this activity, the DRPM is used as a test platform for benchmarking and evaluation. During the demo session, the scrubbing and processing performance of the DRPM is demonstrated, streaming a sequence of images thought the SpaceWire and SpaceFibre interfaces.

Primary author

Mr Dario Cozzi (Bielefeld University)

Co-authors

Mr Dirk Jungewelter (Bielefeld University) Mr Jens Hagemeyer (Bielefeld University) Mr Mario Porrmann (Bielefeld University) Mr Sebastian Korf (Bielefeld University)

Presentation materials