SEFUW: SpacE FPGA Users Workshop, 2nd Edition

From Rosetta to current developments using FPGAs for scientific space missions

16 Sept 2014, 15:00

30m

Newton 2 (European Space Research and Technology Centre (ESTEC))

Design for Space Applications: Fault Tolerance Methodologies

Speaker

Mr Tobias Lange (IDA, TU Braunschweig)

Description

More than one and a half decade ago, the Data Processing Unit (DPU) of the Rosetta Orbiter Spectrometer for Ion and Neutral Analysis (ROSINA) instrument was developed at IDA using a processor system and 6 Actel RT14100A devices, providing a total capacity of only about 8k logic modules with fixed functionality. Nowadays, the DPU for the Polarimetric and Helioseismic Imager (PHI) instrument on Solar Orbiter will have a total capacity of more than 140k logic cells with even higher functionality and embedded memory, which also shows the dramatically increased complexity of such a development. Additionally, almost the complete functionality is reconfigurable during flight by using radiation tolerant SRAM-based Xilinx FPGAs. This is necessary to cope with the demanding on-board processing capabilities, i.e. to handle very high data rates, extract and process final physical values by an autonomous, intelligent, and reliable application already on-board the spacecraft, and adapting itself to the changing mission needs. Classical ground-processing steps need to be performed on-board, making this a design driver for future robotic missions and planetary landers. The benefits of such an adaptable processing platform are a superior data yield and a reduced risk of a total instrument loss. An additional advantage of adaptability is the possibility to time-share resources for a more efficient hardware and power utilization, when dedicated functions are not necessary at the same time. After having demonstrated the successful usage of SRAM-based FPGAs for scientific instruments with the SRAM FPGA-based computer for the Venus Monitoring Camera (VMC) on Venus Express, the first development using in-flight reconfigurability is currently done for the PHI instrument on Solar Orbiter. PHI will provide maps of the continuum intensity, the magnetic field vector and the Line-Of-Sight velocity in the solar photosphere. The polarimeter measurement technique of PHI is ideally suited to apply a robust and reliable technique to obtain maps of the physical quantities already on-board. A non-linear, least square, iterative process is used for this Radiative Transfer Equation (RTE) inversion, which is utilizing the parallel structures of FPGAs to speed up processing. Additionally to the implementation of the FPGA configuration, a mission specific qualification for assembly of the ceramic flip-chip column grid array (CF) package of the used Xilinx device is performed since no qualified process manufacturer for such an assembly was available in Europe. The basic architecture of the PHI DPU design is based on the results of the ESA study for a Dynamically Reconfigurable Processing Module (DRPM). A modular processing system based on SpaceWire communication, featuring an ASIC processor as system controller, a static configuration controller FPGA and two reconfigurable SRAM-based FPGAs was built in the scope of investigating in-flight dynamic partial reconfiguration of FPGA technology, which was a joint effort of Astrium Ltd. and IDA. Within the framework of the DFG research unit Controlling Concurrent Change (CCC) at TU Braunschweig, we are developing a controlled change application using reconfigurable FPGAs under the challenging constraints of space missions. The exchange of single modules has to be possible without modifying the overall system, i.e. without degrading the once achieved qualification for functionality, performance and external behavior. The primary objective is to demonstrate usability and capabilities of autonomy using the mechanisms developed in CCC under the safety, reliability and availability requirements of a typical space application in order to maximize the use of resource limited HW platforms in a multi-functional and adaptable manner. Reconfigurable SRAM-based FPGAs are very susceptible to radiation effects and the system reliability and qualification has to be guaranteed in the harsh space environment. Therefore, the PHI DPU will be equipped with dedicated mitigation techniques against SEEs (Single Event Effects), such as read back scrubbing via JTAG. Further details will be given during presentation, together with some general design issues and tools.

Presentation materials

Slides

SEFUW2014_IDA.pdf