Speaker
Mr
Gianluca Furano
(ESA)
Description
ESA path towards high capacity Flash-based FPGA started few years ago with large number of independent radiation tests in dynamic mode to compare their behaviour with established one-time-programmable antifuse-based solutions. Thanks to radhard by-design (RHBD) techniques and specific validation procedures, those devices can be made at least as resilient with respect to Single Event Upsets (SEU) as the antifuse. This paper will show how the grade of reliability is dependent on the fault-tolerant techniques applied to the logic and the expected performances and design overheads of the logic itself. The definition of the target envirioments, design margins and trade-offs for use of RHBD techniques in space-borne Flash FPGAs as well as the Single Event Upsets mitigation techniques necessary will be presented. A specific tailoring for Flash-based FPGAs for the standard development flow for space-grade designs will be proposed, and the advantages with respect to development risk mitigation discussed. If correctly managed, the overheads inferred by RHBD techniques and controlled development flow instead of becoming an additional design hurdle, may allow the exploit of the greater flexibility and performances of Flash FPGAs with respect to antifuse.
Primary authors
Dr
Alessandra Menicucci
(ESA/ESTEC)
Mr
Carlos Urbina-Ortega
(ESA)
Mr
David Merodio Codinachs
(ESA)
Mr
Gianluca Furano
(ESA)
Mr
Giorgio Magistrati
(ESA/Data Systems Division)
Mr
Kostas Marinis
(ESA)
Mr
Marco Rovatti
(ESA)
Dr
Richard Jansen
(ESA)
