Conveners
Design for Space Applications: Fault Tolerance Methodologies
- David Dangla (CNES)
Design for Space Applications: Fault Tolerance Methodologies
- David Dangla (CNES)
Design for Space Applications: Fault Tolerance Methodologies
- Jelle Poupaert (ESA)
Dr
George Lentaris
(National Technical University of Athens, Greece)
16/09/2014, 14:00
Future planetary exploration will rely on autonomous space rovers with increased moving speed and highly accurate visual odometry algorithms. ESA estimates that the 2020+ Mars missions will involve stereo cameras on robots moving at 6cm/s and calculating high definition depth maps in less than 20sec. Moreover, the error of these processes shall be less than 2m when traveling 100m paths and...
Mr
Dario Cozzi
(Bielefeld University)
16/09/2014, 14:30
Reconfigurable hardware is gaining a steadily growing interest in the domain of space applications. The ability to reconfigure the information processing infrastructure at runtime together with the high computational power of today’s FPGA architectures at relatively low power makes these devices interesting candidates for data processing in space applications. Partial dynamic reconfiguration...
Mr
Tobias Lange
(IDA, TU Braunschweig)
16/09/2014, 15:00
More than one and a half decade ago, the Data Processing Unit (DPU) of the Rosetta Orbiter Spectrometer for Ion and Neutral Analysis (ROSINA) instrument was developed at IDA using a processor system and 6 Actel RT14100A devices, providing a total capacity of only about 8k logic modules with fixed functionality. Nowadays, the DPU for the Polarimetric and Helioseismic Imager (PHI) instrument on...
Dr
Giovanni Beltrame
(Polytechnique Montreal)
17/09/2014, 14:10
Particle and ionizing radiation can alter and severely disrupt the normal behavior of electronics, and lead to their premature failure. For this reason, computing systems for space applications have to be designed using methodologies to mitigate such issues. Field Programmable Gate Arrays (FPGAs) provided with reconfiguration capabilities can facilitate the implementation of fault-mitigation...
Mr
Robért Glein
(Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU))
18/09/2014, 11:10
In order to design a reliable FPGA system as a satellite On-Board Processor, firmware designers have to take Single Event Effects into account. Mitigation schemes (Triple Modular Redundancy, Algorithm-Based Fault Tolerance, …) ease the consequences of this effects. The main disadvantages of these mitigation schemes in FPGAs are resource overhead and additional path delay, depended on the type...
Mr
David Merodio Codinachs
(ESA)
18/09/2014, 12:10
The use of SRAM-based FPGAs in space equipment is growing. Their radiation-hardness needs to be assessed for the final application (i.e. design) that is implemented in the FPGA device.
The talk proposes an approach for FPGA designers to predict the SEE rates during the design activities. The first step addresses the computation of the static SEE rates of each architectural block of the FPGA...
