Speaker
Dr
Rajan Bedi
(Spacechips Ltd.)
Description
The number and diversity of space-grade FPGAs offer many options when architecting satellite sub-systems. One-time programmable anti-fuse, flash and SRAM-based technologies, each with unique fabrics, present many interesting trade-offs when selecting the most appropriate device for your next mission.
Today, space-grade FPGAs are formally available from 350 µm to 28 nm nodes with advertised speeds ranging from 50 to 800 MHz. On-board storage varies from 55 kB to 50 MB with the latest devices offering high-speed serial links with data rates of 8.5 Gbps.
For some spacecraft sub-systems, *e.g.* high throughput payloads or localised control of a power supply, the system requirements quickly dictate the choice of FPGA. For some satellites, OEMs have re-used devices from previous programs which in some cases has proven to be cost effective, however, for others, this decision has resulted in expensive re-design, late delivery of hardware and over-budget projects.
To avoid unnecessary over-design, some manufacturers of satellite sub-systems have started to compare space-grade FPGAs during the system architecture phase to allow them to make an informed decision and select the most appropriate device given their mission constraints, *e.g.* power consumption, cost, performance, reliability etc ...
FPGA vendors offer unique device fabrics with each supplier promoting differently the capability and the number of logic resources offered by their parts. Which FPGA is the most appropriate for your next mission? This paper compares the FPGA implementation of IP used by the space industry and offers an independent view of selecting the right device for your next spacecraft sub-system.
Primary author
Dr
Rajan Bedi
(Spacechips Ltd.)
