Speaker
Mr
Chris McClements
(STAR-Dundee)
Description
To explore the implementation of SpaceFibre and SpaceWire in the new Microsemi RTG4 FPGA, a demonstration system has been developed which implements the STAR-Dundee SpaceWire and SpaceFibre IP cores on the RTG4 development kit. In addition to the RTG4 development kit, the demonstration system uses the STAR-Dundee SpaceFibre and SpaceWire FMC interface card, STAR Fire SpaceFibre interface and diagnostics unit, and a SpaceWire Brick Mk3 USB. The system interconnects between RTG4 development boards using the SpaceFibre and SpaceWire interfaces of the FMC interface boards. Each FMC board features two SpaceFibre interfaces and four SpaceWire interfaces.
The RTG4 FPGA design has two SpaceFibre interfaces running at a bit rate of 2.5 Gbit/s and four SpaceWire interfaces running at 200 Mbit/s. The SpaceFibre interfaces are configured with eight virtual channels, with virtual channels 0 to 3 connected to the SpaceWire interfaces on one interface and virtual channels 4 to 7 interconnected between the SpaceFibre interfaces. The design makes use of the new features of the RTG4 including the SpaceWire clock recovery circuit and the high speed SERDES interfaces. The demonstrator system uses a STAR Fire as a high speed SpaceFibre data generator sending and receiving data through the RTG4 boards to saturate the SpaceFibre link. Another STAR Fire unit can be used in analyser mode to capture data travelling over SpaceFibre. In parallel, one Brick Mk3 is used as a lower speed SpaceWire data source, sending data in one direction to a remote computer. At the same time, this remote computer is sending a webcam video feed through SpaceWire back to the SpaceWire source PC. The low speed SpaceWire traffic generated by the Brick MK3 is sent and received over the same SpaceFibre link as the high speed data traffic. Thanks to the inbuilt QoS for every virtual channel, the low speed traffic is not affected by the high speed traffic used to saturate the link, as they travel over different virtual channels.
The use of the RTG4 with the SpaceFibre and SpaceWire IP cores provides a powerful platform for future spacecraft on-board instrument control, data handling and data processing. Furthermore, due to the inbuilt Quality of Service (QoS) and Fault Detection and Isolation (FDIR) capabilities, SpaceFibre allows the reduction of system complexity, deterministic data delivery and the substantial reduction of cable harness mass.
Summary
To explore the implementation of SpaceFibre and SpaceWire in the new Microsemi RTG4 FPGA, a demonstration system has been developed which implements the STAR-Dundee SpaceWire and SpaceFibre IP cores on the RTG4 development kit. The RTG4 FPGA design has two SpaceFibre interfaces running at a bit rate of 2.5 Gbit/s and four SpaceWire interfaces running at 200 Mbit/s. The SpaceFibre interfaces are configured with eight virtual channels, with virtual channels 0 to 3 connected to the SpaceWire interfaces on one interface and virtual channels 4 to 7 interconnected between the SpaceFibre interfaces. The design makes use of the new features of the RTG4 including the SpaceWire clock recovery circuit and the high speed SERDES interfaces.
Primary author
Mr
Chris McClements
(STAR-Dundee)
Co-authors
Mr
Albert Ferrer
(Star Dundee)
Dr
Alberto Gonzalez Villafranca
(STAR-Dundee Ltd)
Prof.
Steve Parkes
(University of Dundee)
