Speaker
Dr
Nektarios Kranitis
(Dept. of Informatics & Telecommunications, National and Kapodistrian University of Athens)
Description
The huge volume of remote sensing data generated from today’s and future high resolution, high-speed, imagers and the limited spacecraft data storage resources and downlink bandwidth make on-board image compression one of the most challenging on-board payload data processing tasks. Over the last few years, the Consultative Committee for Space Data Systems (CCSDS) issued two image compression standards: a) the CCSDS-122.0-B-1 Image Data Compression (IDC) standard for lossless and lossy (rate-limited and quality-limited) compression of monoband images and b) the CCSDS 123.0-B-1 Lossless Multispectral & Hyperspectral Image Compression standard for lossless compression of Multispectral and Hyperspectral images. These two CCSDS algorithms were developed specifically for use on-board a space platform, addressing challenges related to memory and computational resources requirements achieving an excellent trade-off between compression effectiveness and computational complexity. Currently, CCSDS is working towards the definition of lossy multispectral and hyperspectral compression algorithms either by defining a spectral transform preprocessing stage followed by application of the image compressor defined in CCSDS-122.0-B-1 or extending CCSDS 123.0-B-1 by defining a quantization feedback loop and associated output data structures to provide low-complexity near-lossless compression.
The current state-of-the-art SRAM-based FGPA technology offers radiation hardening by design (RHBD), high density and dynamic partial reconfiguration for in-flight adaptability and Time-Space Partitioning (TSP) of on-board data processing. Such FPGA technology offers unique advantages over both OTP FPGAs and ASICs and can be considered as an excellent platform for implementation of on-board payload data processing due to its ability to support upgrades after launch, greatly enhancing mission profile and extending valuable system life time.
In this presentation, we will present two state-of-the-art throughput performance implementations of both CCSDS image compression standards targeting the Xilinx Virtex-5QV space-grade SRAM FPGA.
The CCSDS-IDC implementation as an IP core is a highly integrated, single FPGA solution providing state-of-the-art throughput performance (128 MSamples/s) and has the following features: a) it does not require any external memory for data buffering; b) it provides high rate-distortion performance for lossy mode supporting large values of segment size (S=128); c) it supports selective image compression by leveraging segmentation features of CCSDS-IDC in order to enable a non-uniform distribution of the available bit budget (i.e. image quality) between a selected region-of-interest (ROI) and the rest of the image, without any modifications on the standard and without any computational performance overhead. The presented CCSDS 122.0-B-1 implementation as an IP core achieves significant throughput performance improvement (128MSamples/s) with respect to the current state-of-the-art (78MSamples/s) and requires about 60% of slices and 67% of BRAMs of the Virtex-5QV FPGA resources.
The CCSDS 123.0-B-1 implementation as an IP core over doubles the throughput performance (100MSamples/s) with respect to the current state-of-the-art (40MSamples/s) and has the following features: a) it supports Band-Interleaved Pixels (BIP) ordering, b) it interfaces with an external DRAM memory controller for data buffering; c) it requires less than 22% of slices and 10% of BRAM of the Virtex-5QV FPGA resources.
To the best of our knowledge, both implementations are the fastest space-grade SRAM FPGA implementations of CCSDS image compression algorithms to date.
Primary authors
Prof.
Antonis Paschalis
(Dept. of Informatics & Telecommunications, National and Kapodistrian University of Athens)
Mr
Antonis Tsigkanos
(Dept. of Informatics & Telecommunications, National and Kapodistrian University of Athens)
Dr
George Theodorou
(Dept. of Informatics & Telecommunications, National and Kapodistrian University of Athens)
Dr
Nektarios Kranitis
(Dept. of Informatics & Telecommunications, National and Kapodistrian University of Athens)
