Speaker
Mr
Jan Andersson
(Aeroflex Gaisler)
Description
The Controller Area Network (CAN) was initially created for automotive applications as a method for enabling robust serial communication. The CAN bus was identified by the European Space Agency (ESA) as a possible replacement for the On-Board Data Handling (OBDH) bus in the late '90s, with the SMART-1 satellite as the first successful example of its usage in an ESA mission. Although the OBDH bus was not immediately abandoned it has been slowly phased out, but not directly to the benefit of the CAN bus, while more to the MIL-STD-1553B bus. Despite the fact that several flight ready components implement the CAN bus protocol, it has taken some time for the CAN bus to get real traction in Europe and the rest of the world. We are currently on the brink of a breakthrough for usage of CAN technology in space and Aeroflex Gaisler has been preparing itself for this moment in time by developing a large set of CAN products ranging from soft IP cores to rad-hard flight components, and from powerful software drivers to handy hardware debuggers and emulation systems such as RASTA. The CAN IP cores have been used in notable ASIC developments (GR712RC, UT699/UT700, AT9713E, COLE) as well as in custom FPGA developments targeting missions such as ExoMars, Sentinel, ISS etc. With the advent of the new flexible data rate concept these IP cores are to be improved to fully support CAN-FD and to provide additional services such as hardware assisted message filtering, in addition to the existing programmable DMA functionality and support for highly accurate time distribution, all to off-load the processor in highly integrated system-on-chip designs where network management is implemented. The ESA on-board reference network is a marriage between the high-speed backbone SpaceWire network and the low-speed spacecraft control bus based on the CAN bus. This has been the continuous target for our developments, always implementing both interfaces in the aforementioned ASICs, all based on our existing IP cores. The new features of the soft IP cores will of course also be included in all future rad-hard ASIC developments.
