Speaker
Description
We introduce the first RISC-V orbital laboratory for microarchitecture fault-tolerance evaluation. The project builds on the space-qualified PULPino-compatible processor cores, belonging to the Klessydra core family, preliminarily introduced at the June 2019 RISC-V workshop. In small satellites, the use of Commercial Off-the-Shelf (COTS) components is increasingly interesting, along with the adoption of an open and extendable instruction set architecture like RISC-V. Fault-tolerant architecture techniques are essential, since COTS components are not intrinsically protected from the harsh space environment at physical level. Furthermore, the possibility of soft-cores implemented in FPGAs opens the way to dynamically adapting the system to harsh environment effects. The presentation addresses an extensive set of fault tolerance techniques, explicitly tailored to RISC-V and leveraging the inherent multi-threaded execution of the Klessydra microarchitecture. In addition to simulation-based and in-lab hardware-based fault-injection, the RISC-V Klessydra Orbital Lab (RV-KOL) is being set up to dynamically analyse the behaviour of the different techniques in a real space environment. The orbital lab will be the payload board launched on a space satellite, designed to be configured “Over-the-Air” (OTA). It can communicate through several standard interfaces and can run processing routines on data coming from on-board sensors. The launch of the PocketQube satellite with RV-KOL payload is expected in mid 2020, through the new European launch system VEGA-C.
