Speaker
Description
The increased complexity of computer-vision algorithms in space on-board applications and also the data fusion of measurements acquired from various on-board instruments and sensors (e.g. LIDAR and hyperspectral images) mandate the development and use of high-performance avionics to provide one or two order of magnitude faster execution than today's conventional space-grade processors and even those marked as “new-space” COTS or rad-tol ones. With this in mind, GMV provides Vision-Based Navigation solutions from concept to implementation, including SW and HW developments. The HW development includes co-processor avionics based on FPGA for HW acceleration of the most demanding algorithmic parts, normally devoted to the computer-vision modules. GMV is developing different HW co-processor versions in the form of Image Processing Unit board (IPU / IPB), or combination of IPU and Interface Controller Units or even a combination of Navigation Camera and IPU into one embedded unique enclosure. A key goal of this solutions is performance per watt ratio to reduce processing units’ power consumption maximizing the processing performance capabilities.
One example is the HERA-IPU. GMV is in charge of developing the GNC subsystem of HERA mission, currently going through Phase C. The HERA Image Processing Unit provides isolation of Image Processing Function and Interfaces Function, as it is relying on a two FPGAs architecture. The design and development of the computer-vision algorithms for HERA IPU are facilitated by the architectural design of the processing FPGA code, which provides an internal interfacing wrapper to integrate the required image processing module satisfying a client-consumer simple interface. HERA IPU also includes pre-processing functions for the image received from navigation camera and allow FPGA reprogramming in-flight to accommodate different image processing algorithms that may be required for different mission phases. The two FPGAs included by HERA IPU allow flexibility, scalability and many options for the design and implementation of complex functionalities, such as high-data rate interfaces management and hardware accelerators. Different computer-vision accelerators which are not used in the same moment of time can be used during the mission by replacing bitstreams in the processing FPGA in-flight to save a potentially needed second FPGA unit
In addition to HERA-IPU, a parallel IPU development named GMVision board offers a highly versatile space oriented Image Processing Unit (IPU) fully redundant, with spacewire interfaces to redundant Narrow-Angle Camera and redundant Wide-Angle Camera. The main electronics are fully European rad-hard components as the BRAVE NG-MEDIUM, NG-LARGE or ArcPower DC-DC converters. This technology development program board is being validated for Descent & Landing scenario, for Rendezvous operations and for long-range detection. The project includes the FPGA code development of 4 different image processing techniques used in the presented navigation scenarios. Similar concept is presented for Multispectral Rendezvous Navigation, including a HW/SW solution combining LEON4 processor and NG-LARGE FPGA co-processors.
GMV IPU, IPCU, ICU avionics equipment with direct applicability for HERA mission can easily be re-used or adapted for other space missions such as ADR, Space Exploration, Satellite Servicing, Debris Tracking/Monitoring or even scientific purposes.
