The 16th ESA Workshop on Avionics, Data, Control and Software Systems (ADCSS) covers topics related to avionics for space applications, in the form 5 sessions throughout 3 days. The workshop acts as a forum for the presentation of position papers followed by discussion and interaction between ESA and Industry and between participants. Each theme part of ADCSS workshops will be first introduced and then expanded by presentations on related developments from technical and programmatic points of view. A round table discussion may follow, concluded by a synthesis outlining further actions and roadmaps for potential inclusion into ESA’s technology R&D plans.
Over the 3 days, the following sessions are foreseen:
The objective of this annual SAVOIR session is to update the avionics stakeholders with the progress done over the last year and to discuss the next steps. The workshop will focus on status of the working groups, SAVOIR related topics and technology planning.
Session 1: On-board processing and co-processing
The increase in data rates from new sensors pose a challenge across the data handling and processing chain. The payload data handling system needs to receive, process, store and transmit data at multiple gigabits per second -- which will require the use of new components (interfaces, FPGAs, processors, memories, etc). In this session the presentations will cover the end-to-end space segment targeting on-board data handling and processing chains for high-rate EO and scientific payloads, including new sensors with high-speed serial links; mass-memories; DPUs for on-board processing (OBP) and AI; and high-rate optical and RF down-links.
Session 2: GNC – New generation of inertial sensors
During the GNC - New generation of inertial sensors session major European companies will present the state of art on inertial sensors and inertial measurement units for guidance, navigation and control of spacecrafts. Innovation in GNC is focused on miniaturization, reducing power and add computational resources of existing technology in order ease the control system development and to provide precise and reliable data to successfully drive satellites until mission's end-of-life.
Session 3: Processor architectures & SW supporting multi core
Nowadays, multicore on-board computing is a must in currently developed S/Cs. SPARC, ARM and the promising RISC-V ISAs are co-living in the market, and this session is dedicated to Multi-Core Processor Instruction Set Architectures (ISA), accelerators and respective SW ecosystems. Different manufacturers, primes and agencies are invited to present their overview and opinion on the matter, along with their related HW products, SW ecosystems, and ongoing and future activities.
Session 4: Functional verification
On top of the workshop presentations, a number of booths from various European manufacturers will be available for the public, including Microchip, NanoExplore or Cobham.