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EDHPC 2023 - European Data Handling & Data Processing Conference

Oct 2 – 6, 2023
ANTIPOLIS - Palais des Congrès d'Antibes
Europe/Amsterdam timezone

EDHPC Organising Committee

Session

DFTS

Oct 3, 2023, 9:00 AM
Salle Miles Davis

Salle Miles Davis

Conveners

DFTS: Session 1: Reliable and Secure Deep Neural Networks

  • Matteo Sonza Reorda

DFTS: Session 2: Advanced Testing and Validation Techniques

  • Athanasios Papadimitriou

DFTS: Session 3: Protecting Accelerators and Microprocessors against hardware attacks

  • Haralampos Stratigopoulos

DFTS: Session 4: Defects, Errors and Aging

  • Elena-Ioana Vatajelu

DFTS: Special Session #1 - Safety and Security Assessment through X-Ray Illumination

  • Paolo Maistri

DFTS: Special Session #2 - Reliability of Microcontrollers in Radiation Harsh Environment at Different Levels of Abstraction. The Case Study of the HARV RISC-V SoC

  • Luigi Di Lillo

DFTS: Keynote 2: Radiation Effects in FPGA and SoCs

  • Gianluca Furano (ESA/Data Systems Division)
  • Pierre Maillard (AMD, INc.)

DFTS: Keynote 1: Secure SoC Development Lifecycle: Challenges and Solutions (Prof. Mark M. Tehranipoor)

  • Marco Ottavi (UTWENTE)
  • Mark Tehranipoor (Intel/U Florida)

DFTS: Opening

  • Marco Ottavi (UTWENTE)
  • Gianluca Furano (ESA/Data Systems Division)

Description

Opening remarks

Presentation materials

DFTS-MT-2023.pptx
  1. 207. Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint Template. Rahul Chaurasia, Abhinav Reddy Asireddy and Anirban Sengupta
    Rahul Chaurasia
    10/3/23, 10:50 AM
    Presentation
  2. 208. EnSAFe: Enabling Sustainable SoC Security Auditing using eFPGA-based Accelerators., Mridha Md Mashahedur Rahman, Shams Tarek, Kimia Zamiri Azar and Farimah Farahmandi
    Farimah Farahmandi
    10/3/23, 11:10 AM
    Presentation
  3. 209. Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes., Alessandro Palumbo, Luca Cassano, Pedro Reviriego and Marco Ottavi
    Luca Cassano
    10/3/23, 11:30 AM
    Presentation
  4. 210. Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses., Alessandro Palumbo, Marco Ottavi and Luca Cassano
    Marco Ottavi (UTWENTE)
    10/3/23, 11:50 AM
  5. 258. On Attacking Scan-based Logic Locking Schemes., Govind Rajhans Jadhav, Sonali Shukla and Virendra Singh
    Virendra Singh
    10/3/23, 12:00 PM
    Presentation
  6. 211. An Efficient Security Closure Methodology for EM-based Attacks on Power Grid Structures., Alexandra Takou, Pavlos Stoikos, Moysis Moysis, George Floros, Nestor Evmorfopoulos and Georgios Stamoulis
    Alexandra Takou
    10/3/23, 12:10 PM
    Presentation
  7. 212. A Self Aware Security Approach for Real Time Neural Network Applications from Row Hammer Attacks in Multi FPGA Multi User Environment., Krishnendu Guha and Gouriprasad Bhattacharyya
    Krishnendu Guha
    10/3/23, 12:20 PM
    Presentation
  8. 213. An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers., Toshinori Hosokawa, Kyohei Iizuka and Masayoshi Yoshimura
    Toshinori Hosokawa
    10/3/23, 2:00 PM
    Presentation
  9. 214. A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and to Improve Gate Exhaustive Fault Coverage., Momona Mizota, Toshinori Hosokawa, Masayoshi Yoshimura and Masayuki Arai
    Momona Mizota
    10/3/23, 2:20 PM
    Presentation
  10. 215. Evaluating the Impact of Aging on Path-Delay Self-Test Libraries., Lorena Anghel, Riccardo Cantoro, Michele Portolan, Sandro Sartoni and Matteo Sonza Reorda
    Sandro Sartoni
    10/3/23, 2:40 PM
    Presentation
  11. 216. An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing., Yudai Toyooka, Haruki Watanabe, Toshinori Hosokawa and Masayoshi Yoshimura
    Masayoshi Yoshimura
    10/3/23, 3:00 PM
    Presentation
  12. 217. Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story., Francisco Fuentes, Sergi Alcaide, Raimon Casanova and Jaume Abella.
    Francisco Fuentes
    10/3/23, 3:10 PM
    Presentation
  13. 218. Partial Triple Modular Redundancy (TMR) Method for Fault-Tolerant Circuit based on HITS Algorithm., Yu Xie, Wen-Yue Yu, Ning Zhang, He Chen and Yi-Zhuang Xie
    Ning Zhang
    10/3/23, 3:20 PM
    Presentation
  14. 219. Gradient Descent Iterative Correction Unit for Fixed Point Parity Based Codes., Oana Boncalo and Alexandru Amaricai
    Oana Boncalo
    10/3/23, 3:30 PM
    Presentation
  15. 220. Analyzing the Reliability of Alternative Convolution Implementations for Deep Learning Applications., Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Nazzari and Dario Passarello
    Luca Cassano
    10/3/23, 4:10 PM
    Presentation
  16. 221. Uncovering hidden vulnerabilities in DNNs through evolutionary-based Image Test Libraries., Vittorio Turco, Annachiara Ruospo, Gabriele Gavarini, Ernesto Sanchez and Matteo Sonza Reorda
    Matteo Sonza Reorda
    10/3/23, 4:30 PM
    Presentation
  17. 222. Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator., Salvatore Pappalardo, Ali Piri, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Alberto Bosio and Ernesto Sanchez
    Salvatore Pappalardo
    10/3/23, 4:50 PM
    Presentation
  18. 223. Analysis and Improvement of Resilience for Long Short-Term Memory Neural Networks., Mohammad Hasan Ahmadilivani, Jaan Raik, Masoud Daneshtalab and Alar Kuusik
    Mohammad Hasan Ahmadilivani
    10/3/23, 5:10 PM
  19. 224. Highly Efficient Layered Syndrome-based Double Error Correction Utilizing Current Summing in RRAM Cells to Simplify Decoder, Shruti Dutta, Sai Charan Rachamadugu Chinni, Abhishek Das and Nur Touba
    Nur Touba
    10/4/23, 10:50 AM
    Presentation
  20. 225. DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture., Raghunandana K K, Yogesh Prasad K R, Matteo Sonza Reorda and Virendra Singh
    Raghunandana K K
    10/4/23, 11:10 AM
    Presentation
  21. 226. Image Degradation in Time Due to Interacting Hot Pixels., Glenn Chapman, Li-Yu Wu, Israel Koren, Zahava Koren and Klinsmann J. Coelho Silva Menes
    Glenn Chapman
    10/4/23, 11:30 AM
    Presentation
  22. 227. An Estimation Method of Defect Types Using Artificial Neural Networks and Fault Detection Information., Natsuki Ota, Toshinori Hosokawa, Koji Yamazaki, Yukari Yamauchi and Masayuki Arai
    Masayuki Arai
    10/4/23, 11:50 AM
    Presentation
  23. 228. An efficient High-Volume Production Performance Screening using On-Chip Ring Oscillators., Tobias Kilian, Abhishek Sengupta, Daniel Tille, Martin Huch and Ulf Schlichtmann
    Tobias Kilian
    10/4/23, 12:10 PM
    Presentation
  24. 230. Soft-SoC Robustness Evaluation using X-Rays: a Case Study and Differences with other Beams
    Luc Noizette
    10/4/23, 2:00 PM
  25. 231. X ray nanoprobe for fault attacks and circuit edits on 28-nm integrated circuits
    Laurent Maingault
    10/4/23, 2:20 PM
  26. 232. Simulation Methodology for Assessing X-Ray Effects on Digital Circuits
    Paolo Maistri
    10/4/23, 2:40 PM
  27. 233. Characterization of a Fault-Tolerant RISC-V System-on-Chip for Space Environments
    Andre Martins Pio d Mattos
    10/4/23, 3:00 PM
    Presentation
  28. 234. Implementation and Reliability Evaluation of a Vector Extension for a RISC-V System-on-Chip
    Carolina Imianosky
    10/4/23, 3:20 PM
    Presentation
  29. 235. Hardening a Real-Time Operating System for a Dependable RISC-V System-on-Chip
    Douglas Almeida dos Santos
    10/4/23, 3:40 PM
    Presentation
  30. 229. The use of synchrotron light as an alternative to assess the Single Event Effects induced by Heavy Ions in electronic circuits
Building timetable...