EDHPC 2023 - European Data Handling & Data Processing Conference

Europe/Amsterdam
ANTIPOLIS - Palais des Congrès d'Antibes

ANTIPOLIS - Palais des Congrès d'Antibes

60 Chem. des Sables 06160 Antibes France
Description

EDHPC 2023

The first European Data Handling & Data Processing ConferenceEDHPC 2023 – will be held from the 2nd to the 6th of October 2023 in Juan-Les-Pins (French Riviera). It is organised by the European Space Agency (ESA), with the support of the local tourist office. Find the latest information on the official website.

Congratulations to all authors whose digests have been accepted. 

 

  • For all main authors / presenters:

- please register on the official EDHPC website as soon as possible (deadline was 30th June 2023).

- please submit your final paper and copyright form before the 25th of August 2023.

  • For presenters at an oral session, please submit your slides before the 15th of September 2023.
  • For presenters at the poster session, please bring your printed poster (A0 portrait format) at the EDHPC and dispose it in the poster area of the conference venue before Monday 2nd of October, lunch time.

Final Submission Instructions

 

Please be aware that the proceedings will be published on IEEE Explore and will have to conform to the IEEE publication standard. Please find the submission instructions and submission page here.

 

Additional presenter instructions (both oral and poster) can be found on the Presenter Instructions page.

 

 

EDHPC Organising Committee
    • 6:00 PM
      Welcome / Pre-Registration Drink - Espace Méditerranée Espace Gould

      Espace Gould

    • Keynote Presentations: Part I Auditiorium

      Auditiorium

      • 1
        Welcome and Introduction
        Speakers: Ali Zadeh (ESA), Olivier Mourra (ESA-ESTEC- TEC directorate - Head of On-Board Computer & Data Handling Systems Section), Mr Piero Angeletti (ESA)
      • 2
        Computing platform technologies of interest for the European Space industry

        About the Key Note: With the megatrend of digitalization of satellites, the Space industry is jumping into the Moore’s law.
        If Personal Computers coming into everyone’s home and now powerful Smartphone being in everyone’s hands have fully enjoy the Moore’s Law dynamic for decades, the Space industry is now facing a new paradigm of exponential development cost trend, increasing security breaches and challenges to secure critical technologies supply.
        The speech will present the dynamic of computing platform technologies of interest for the European Space industry.

        About the Presenter: Francois Martin is a senior semiconductor expert at STMicroelectronics who created in 2016, a dedicated ASIC activity, addressing the Space & Defense market, with a primary focus on European critical projects & programs. After more decades spent introducing innovative Bicmos technologies into mobile phones, he joined the core team that brought the innovative FD-SOI technology to several markets, from smartphone to Satellites processing equipments.

        Speaker: Mr Francois Martin (STM)
      • 3
        JPL Ingenuity Mars Helicopter

        About the Keynote: The Ingenuity Mars Helicopter is the first aircraft to operate from the surface of another planet, having travelled to Mars as part of NASA’s Mars 2020 mission. In this talk, we will look back at the development of Ingenuity, the ongoing flight operations on Mars, and the impact that Ingenuity has had on the future of Mars exploration. We will focus on key technologies that Ingenuity has pioneered, including the use of commercial off-the-shelf electronics in a planetary exploration context.

        About the Presenter:
        Håvard Grip is a Robotics Technologist at NASA’s Jet Propulsion Laboratory in Southern California. He led the development of Ingenuity’s Aerodynamics & Flight Control system, and served as Chief Pilot during Ingenuity’s first 37 flights. He is currently the Chief Engineer of Autonomy & Aerial Flight for the Mars Sample Recovery Helicopters, part of the joint NASA-ESA Mars Sample Return campaign.

        Speaker: Mr Håvard Grip (JPL)
    • 10:40 AM
      Coffee Break
    • Keynote Presentations: Part II Auditiorium

      Auditiorium

      • 4
        RHA, COTS and their application to new space products

        About the Presenter:
        As the CEO and founder of Aerospacelab, Benoît Deper has been at the helm of the company since 2018. With his recognized experience in the space industry and his knowledge of the major players, this entrepreneur quickly succeeded in gaining the support of solid investors such as Airbus Ventures.
        After graduating from UCLouvain's École polytechnique de Louvain (EPL), Benoît Deper first joined the ranks of two emblematic institutions in the sector: NASA and its European counterpart, ESA, for three years, before going on to become CTO of a Swiss company specializing in space launch, Swiss Space Systems (S3).
        In 2018, Benoît embarked on the great entrepreneurial adventure as he created Aerospacelab. Since then, the company headquartered nearby Brussels (Mont-Saint-Guibert) is steadily increasing and has now over 200 employees. What's next? The inauguration of Aerospacelab’s megafactory in 2025!
        emblematic institutions in the sector: NASA and its European counterpart, ESA, for three years, before going on to become CTO of a Swiss company specializing in space launch, Swiss Space Systems (S3). A career start marked by an entry into NASA's coveted "Ames" ecosystem, the cradle of many aerospace unicorns including American superstar, Planet.

        Speaker: Mr Benoit Deper (Aerospacelab)
      • 5
        A retrospective of some key European achievements in the domain of Spacecraft On-board Data Handling and Data Processing

        About the Keynote:
        Taking the best of dramatically increasing capabilities of on-ground computing solutions while sustaining the space environment and operating with scarce physical sources has been the continuous challenge of spacecraft on-board data handling and processing over the last three decades. The speech will present a retrospective of some key European achievements and will highlight sometimes unexpected converging trends between classical satellites, space infrastructures, launchers and large constellations.

        About the Presenter:
        Remi Roques is Senior Expert Avionics and on-board data handling major spacecraft component manager at Airbus DS Space Systems. His career started in network protocol development research and was followed by many years on the European segment of the ISS (Columbus laboratory, ISS payloads) as system engineer and project manager. He then played an active role in the definition and deployment of several generations of Airbus product lines for data management and processing chains serving both institutional and commercial domains.

        Speaker: Remi Roques (Airbus)
    • 12:30 PM
      Lunch + Exhibition opening
    • EDHPC Tutorial - Lattice: Lattice Semiconductor hands-on tutorial on EDA tools and RISC-V system builder for space grade FPGAs Salle Miles Davis

      Salle Miles Davis

      Introduction
      Embedded system solutions play an important role in FPGA system designs for Space allowing designers to develop software for processors in FPGAs, provides flexibility and in-orbit programmability to implement distributed architectures via system bus.To develop an embedded system on an FPGA, user needs to design the System-on-Chip (SoC) with an embedded processor, develop system software on the processor and implement the complete architecture design in the FPGA.

      Audience
      The intended audience for this hands-on tutorial includes embedded system designers, embedded software developers and FPGA designers.

      What will you learn?
      In this hands-on tutorial you will learn the basics of LATTICE Propel™ and Radiant™ tools while developing a complete reference design.
      Lattice Propel™ helps users develop a system with a RISC-V processor, SpaceWire IP, and a set of embedded tools.
      Lattice Radiant™ helps the FPGA designer implement the developed architecture design.
      No prior knowledge of LATTICE Propel™ and Radiant™ is required. Lattice will provide all required hardware and software for this hand-on tutorial.

      Outline of hands-on tutorial
      The tutorial will guide you through the development of a reference design:

      How to build an embedded design with RISC-V and SpaceWire
      How to develop the software for the processor subsystem
      How to implement the architecture design in the FPGA
      How to debug the system using the Propel™ environment
      

      Note: Installation of software before attending the tutorial
      To prepare for the hands-on tutorial, you need to install LATTICE Propel™ and Radiant™ on your computer prior to the event. LATTICE Propel™ and Radiant™ installation and free license will be provided upon completing your registration for the tutorial.

      Conveners: Mr Fabien Lasvignes (Lattice Semiconductor), Mr Franck Perronnet (Lattice Semiconductor), Jim Tavacoli (Lattice Semiconductor), Mr Marco Boschini (Lattice Semiconductor)
    • EDHPC Tutorial: Artificial Intelligence workflows for FPGA & SoC using a Deep Learning Processor: Part 1 Salle Sidney Bechet

      Salle Sidney Bechet

      Introduction
      Artificial intelligence (AI) is everywhere. The space industry is no exception. Automated recognition of lunar craters for moon landings and identification of space junk using imaging could play important roles in securing space safety and advancing space exploration. Deep Neural Networks (DNN) are the most successful solution for image-based object classification, and for most practical applications it requires performant platforms like FPGAs and SoCs.

      Designing DNNs for embedded devices such as FPGAs and SoCs is challenging because of resource constraints, the complexity of programming in Verilog or VHDL, and the hardware expertise needed for prototyping on an FPGA or SoC.

      Audience
      Engineers who are developing AI algorithms and need to deploy on FPGA/SoC platforms
      Level: both beginner and expert

      What will you learn?
      In this tutorial we will explain:
      - Developing AI models using low code / no code workflows and interoperability with Python based frameworks (TensorFlow and PyTorch).
      - Verifying and validating AI models.
      - Prototyping and integrating Deep Learning-based vision applications using a Deep Learning Processor (DLP).
      - Optimizing model performance on FPGA using compression methods like quantization and pruning.

      Outline of hands-on tutorial
      This tutorial explores developing a Deep Neural Network (DNN) algorithm leveraging FPGAs for space applications. It covers the deployment of DNN on FPGA platforms to accelerate tasks such as image analysis, object recognition, and data processing. Engineers at all skill levels can learn about optimizing, prototyping, and integrating DNN into FPGA-based systems, enabling efficient and high-performance space-related applications.

      Speakers: Stephan van Beek and Pierre Harouimi from Mathworks

      Conveners: Mr Pierre Harouimi (MathWorks), Stephan van Beek (MathWorks)
    • EDHPC Tutorial: Radiation Testing: Radiation Testing Auditorium

      Auditorium

      Introduction
      The tutorial will cover various aspect related to radiation testing and radiation mitigation on On-Board Data Handling and Data Processing Systems. We will cover topics on digital technologies, radiation testing planning and execution, Radiation Hardness Assurance, mitigation techniques and ESA Mission Classification. Special focus will be on complex devices often used in Data Handling and Processing Systems.

      Audience
      All on-board data handling and data processing professionals interested in learning more about different aspects of radiation testing and radiation mitigation in hardware flying on satellites today and in the future.

      What will you learn?
      The tutorial will cover various aspect related to radiation testing in the first part and radiation mitigation in the second part. The radiation testing portion of the tutorial will start with an overview of digital and analogue technologies, focusing on the different options for the space market from David Merodio and Richard Jansen (ESA). Then, we will get a thorough overview of the basic mechanisms of radiation-induced faults in complex devices with an emphasis on COTS component by Dr. Indranil Chatterjee (Airbus). You will learn the basic metrics for setting up successful Single Event Effect (SEE) test campaigns, running the tests and analysing the test data. Finally, you will about the necessity of updating our radiation hardness assurance methods for better characterization of today’s complex system applications by Melanie Berg (Space R2 LLC). The second half of the tutorial will focus on different aspects of radiation effects mitigation in complex COTS devices on both module and component level by Kostas Marinis and Lucana Santos (ESA). Finally, we will learn about the new ESA mission classification, including tailoring of the Q branch and its implications on the different radiation testing requirements including some words about ESA experiences by Viyas Gupta (ESA).

      Speakers: David Merodio (ESA), Richard Jansen (ESA), Dr. Indranil Chatterjee (Airbus), Melanie Berg (Space R2 LLC), Kostas Marinis (ESA), Lucana Santos (ESA), Viyas Gupta (ESA)

      Conveners: Dr Maris Tali (ESA), Richard Jansen (ESA)
      • 7
        Radiation Testing Talk
        Speaker: Richard Jansen (ESA)
      • 8
        Single-Event Effects – Basic Mechanisms and Testing of Complex Devices

        With the “New Space” approach, space is envisioned to become accessible and affordable to all with the development of low-cost satellite systems. A large part of this dream revolves around using commercially available high-performance electronic components and systems. However, a key barrier to the widespread usage of COTS parts in space is the harsh natural radiation environment. In this tutorial, an overview of the single-event effects impacting advanced semiconductor nodes will be discussed. Key metrics for designing SEE tests, such as sample preparation, biasing conditions, thermal impacts, internal fault tolerance mechanisms, etc. will be covered. Being able to determine the interplay of these variables is an integral part of designing a test to meet the needs of a specific mission. The short course will also explore designing test fixtures, selection of test facilities, executing tests, and analyzing test data. Efficacies and limitations of board-level SEE testing, as opposed to component-level SEE testing, for evaluating the vulnerability of COTS components for application in space, will also be discussed.

        Speaker: Dr Indranil Chatterjee (Airbus)
      • 9
        Modernization of Radiation Hardness Assurance Methods for SoC/FPGA Space Applications

        For space systems, radiation particles can cause faults in microelectronics that inhibit operation and hence reduce system reliability. In turn, radiation hardness assurance methods have been developed to predict component susceptibility and perform system failure analyses. These practices have been applied for decades and are now in need of being modernized for better characterization of today’s complex system applications. This presentation describes what is required to test and analyze complex components such as SoC and FPGA devices, how conventional methods are insufficient, and how new methods can provide optimal coverage for failure analyses.

        Speaker: Melanie Berg (Space R2 LLC)
    • EDHPC Tutorial: Satellite Radio Frequency payloads and Instruments – Overview and challenges for data and signal processing: Part 1 Salle Ella Fitzgerald (145)

      Salle Ella Fitzgerald (145)

      Introduction
      The implementation of radar and telecommunication requirements into digital back-end technology demands an increase in bandwidths, more powerful digital data processing, and higher speed interfaces.
      It is nowadays common to see Space-qualified data conversion devices and FPGAs, HSSL capable of converting signals in the GHz range, processing them and transferring them for transmission or further processing of the received data. This allows to move more functions to digital components and an improvement of flexibility from a system perspective.

      This tutorial provides and overview of the most employed hardware architectures in radar and telecommunication payloads. It provides an explanation of the major design trade choices that are typically done when defining a radar system, taking into account the constraints from the existing hardware capabilities as well as missions requirements.

      The first part of this tutorial will describe the end to end architectures of telecommunication payload, focusing on new requirements related to digital beamforming, regenerative processing and 5G protocols.

      The second part of this workshop will describe the end to end architectures of radar payloads, focusing on new requirements for upcoming missions.

      Audience
      The intended audience for this workshop is space industry professionals that want to understand or reflect on the impacts of digital processing functions in radio frequency payloads. The workshop is aimed in particular to suppliers of equipment and components interested in discussing requirements for upcoming missions.

      What will you learn?
      The tutorial will give an overview of end-to-end architecture for radio frequency payloads and highlight the design drivers in digital processors.

      Outline of hands-on tutorial
      This tutorial explores new trends in on-board processing for Radio Frequency Payloads. The main areas of development for upcoming Synthetic Aperture Radar and Telecommunication missions are presented and discussed.

      Speakers: Salvatore D'Addio (ESA), Max Ghiglione (ESA)

      Convener: Mr Salvatore D'Addio (ESA)
    • Exhibition Espace Gould

      Espace Gould

    • 4:00 PM
      Coffee Break
    • EDHPC Tutorial - OBDP: Overview of On-Board Processing Technologies for future missions (ESA) Salle Miles Davis

      Salle Miles Davis

      Introduction
      The tutorial will start by introducing the concept of ESA mission class, followed by a presentation showing the mostly commonly used devices in ESA payloads, onboard computers (OBC) and instruments control unit (ICU). While rad hard parts may not need radiation mitigation techniques at board / equipment level, rad tolerant device on the contrary may require extra care to mitigate “single failure interrupt” (SEFI). SEFI mitigation techniques will be addressed in this presentation.

      Audience
      This tutorial is dedicated to young professionals and companies with limited experience related to space onboard processing technologies. The tutorial will provide the audience with a non-exhaustive but broad overview of the technologies used in ESA class 1,2,3, missions.

      What will you learn?
      Participants will learn about ESA mission class differentiation. Participants will learn about FPGAs, SoC FPGAs and processors used or planned to be used in ESA class 1,2,3 missions. Attendees learn about SEFI mitigation techniques.

      Convener: laurent hili
    • EDHPC Tutorial: Artificial Intelligence workflows for FPGA & SoC using a Deep Learning Processor: Part 2 Salle Sidney Bechet

      Salle Sidney Bechet

      Introduction
      Artificial intelligence (AI) is everywhere. The space industry is no exception. Automated recognition of lunar craters for moon landings and identification of space junk using imaging could play important roles in securing space safety and advancing space exploration. Deep Neural Networks (DNN) are the most successful solution for image-based object classification, and for most practical applications it requires performant platforms like FPGAs and SoCs.

      Designing DNNs for embedded devices such as FPGAs and SoCs is challenging because of resource constraints, the complexity of programming in Verilog or VHDL, and the hardware expertise needed for prototyping on an FPGA or SoC.

      Audience
      Engineers who are developing AI algorithms and need to deploy on FPGA/SoC platforms
      Level: both beginner and expert

      What will you learn?
      In this tutorial we will explain:
      - Developing AI models using low code / no code workflows and interoperability with Python based frameworks (TensorFlow and PyTorch).
      - Verifying and validating AI models.
      - Prototyping and integrating Deep Learning-based vision applications using a Deep Learning Processor (DLP).
      - Optimizing model performance on FPGA using compression methods like quantization and pruning.

      Outline of hands-on tutorial
      This tutorial explores developing a Deep Neural Network (DNN) algorithm leveraging FPGAs for space applications. It covers the deployment of DNN on FPGA platforms to accelerate tasks such as image analysis, object recognition, and data processing. Engineers at all skill levels can learn about optimizing, prototyping, and integrating DNN into FPGA-based systems, enabling efficient and high-performance space-related applications.

      Speakers: Stephan van Beek and Pierre Harouimi from Mathworks

      Conveners: Pierre Harouimi (MathWorks), Stephan van Beek (MathWorks)
    • EDHPC Tutorial: Radiation Testing: Radiation Mitigation Techniques & RHA Auditorium

      Auditorium

      Introduction
      The tutorial will cover various aspect related to radiation testing and radiation mitigation on On-Board Data Handling and Data Processing Systems. We will cover topics on digital technologies, radiation testing planning and execution, Radiation Hardness Assurance, mitigation techniques and ESA Mission Classification. Special focus will be on complex devices often used in Data Handling and Processing Systems.

      Audience
      All on-board data handling and data processing professionals interested in learning more about different aspects of radiation testing and radiation mitigation in hardware flying on satellites today and in the future.

      What will you learn?
      The tutorial will cover various aspect related to radiation testing in the first part and radiation mitigation in the second part. The radiation testing portion of the tutorial will start with an overview of digital and analogue technologies, focusing on the different options for the space market from David Merodio and Richard Jansen (ESA). Then, we will get a thorough overview of the basic mechanisms of radiation-induced faults in complex devices with an emphasis on COTS component by Dr. Indranil Chatterjee (Airbus). You will learn the basic metrics for setting up successful Single Event Effect (SEE) test campaigns, running the tests and analysing the test data. Finally, you will about the necessity of updating our radiation hardness assurance methods for better characterization of today’s complex system applications by Melanie Berg (Space R2 LLC). The second half of the tutorial will focus on different aspects of radiation effects mitigation in complex COTS devices on both module and component level by Kostas Marinis and Lucana Santos (ESA). Finally, we will learn about the new ESA mission classification, including tailoring of the Q branch and its implications on the different radiation testing requirements including some words about ESA experiences by Viyas Gupta (ESA).

      Speakers: David Merodio (ESA), Richard Jansen (ESA), Dr. Indranil Chatterjee (Airbus), Melanie Berg (Space R2 LLC), Kostas Marinis (ESA), Lucana Santos (ESA), Viyas Gupta (ESA)

      Conveners: Dr Maris Tali (ESA), Richard Jansen (ESA)
      • 10
        Radiation Mitigation Talk 1
        Speaker: Kostas Marinis (ESA)
      • 11
        Radiation Mitigation Talk 2
        Speaker: Lucana Santos Falcon (Moltek Consultants Ltd. for European Space Agency)
      • 12
        ESA Mission Classification: focus on RHA tailoring & recommendations for COTS projects

        An overview of the current updates regarding the radiation hardness assurance (RHA) tailoring of each of the ESA mission classes . ESA is now classifying missions according to five classes: “1” being the lowest risk class, down to “5” being the highest risk class. For each mission class, the ECSS requirements are in the process of being tailored including system engineering and product assurance requirements. This talk will briefly introduce the current tailoring with respect to RHA requirements.

        The talk will also include a discussion on the tailoring impact on largely COTS-based projects.

        Examples of RHA activities on COTS-based projects will be provided, as well as some advice and reminders, based on recent experience, primarily focused towards “New Space” companies.

        Speaker: Viyas Gupta (ESA)
    • EDHPC Tutorial: Satellite Radio Frequency payloads and Instruments – Overview and challenges for data and signal processing: Part 2 Salle Ella Fitzgerald (145)

      Salle Ella Fitzgerald (145)

      Introduction
      The implementation of radar and telecommunication requirements into digital back-end technology demands an increase in bandwidths, more powerful digital data processing, and higher speed interfaces.
      It is nowadays common to see Space-qualified data conversion devices and FPGAs, HSSL capable of converting signals in the GHz range, processing them and transferring them for transmission or further processing of the received data. This allows to move more functions to digital components and an improvement of flexibility from a system perspective.

      This tutorial provides and overview of the most employed hardware architectures in radar and telecommunication payloads. It provides an explanation of the major design trade choices that are typically done when defining a radar system, taking into account the constraints from the existing hardware capabilities as well as missions requirements.

      The first part of this tutorial will describe the end to end architectures of telecommunication payload, focusing on new requirements related to digital beamforming, regenerative processing and 5G protocols.

      The second part of this workshop will describe the end to end architectures of radar payloads, focusing on new requirements for upcoming missions.

      Audience
      The intended audience for this workshop is space industry professionals that want to understand or reflect on the impacts of digital processing functions in radio frequency payloads. The workshop is aimed in particular to suppliers of equipment and components interested in discussing requirements for upcoming missions.

      What will you learn?
      The tutorial will give an overview of end-to-end architecture for radio frequency payloads and highlight the design drivers in digital processors.

      Outline of hands-on tutorial
      This tutorial explores new trends in on-board processing for Radio Frequency Payloads. The main areas of development for upcoming Synthetic Aperture Radar and Telecommunication missions are presented and discussed.

      Speakers: Salvatore D'Addio (ESA), Max Ghiglione (ESA)

      Convener: Mr Salvatore D'Addio
    • Exhibition Espace Gould

      Espace Gould

    • 6:00 PM
      Conference Opening Cocktail - Platinum Sponsor announcement: DSI

      Introduction by Felix Siegle (ESA)

    • DFTS: Opening Salle Louis Armstrong

      Salle Louis Armstrong

      Opening remarks

    • Exhibition Espace Gould

      Espace Gould

    • Session 1 - Satellite End-to-end data handling and processing architectures: ESA Missions Auditiorium (TBD)

      Auditiorium (TBD)

      • 13
        End-to-end data processing architecture of the ESA exo-planet hunting mission PLATO
        Speaker: Mr Claas Ziemke (DLR)
      • 14
        Solar Orbiter Data Handling Lessons Learned
        Speakers: Dr Felix Siegle (ESA-ESTEC), Mr Daniel Lakey (ESA-ESOC)
      • 15
        An overview of the electrical, electronic and on-board data handling architecture of the Ariel Payload
        Speaker: Mauro Focardi (INAF/OAA - Osservatorio Astrofisico di Arcetri)
      • 16
        Meteosat Third Generation: Data Handling Architecture of a State-of-the-Art GEO Meteorological Satellite
        Speaker: Alex Palacios (ESA)
    • Session 2 - OBDP: On-Board Processing Applications and Usage in Missions Salle Ella Fitzgerald (145)

      Salle Ella Fitzgerald (145)

      Convener: David Steenari (ESA)
      • 17
        AI uses cases on EO satellites
        Speaker: Olivier Cambon (Airbus Defence and Space)
      • 18
        On-board data processing for meteor detection on SLAVIA mission
        Speakers: Tomáš Kašpárek (BUT FIT), Martin Javorka (Zaitra s.r.o.)
      • 19
        A Dual Camera System with AI enabled Imaging Control for Earth Observation Applications: A Feasibility Study
        Speaker: Mr Mathieu Bernou (OHB Hellas)
      • 20
        Robust Machine Learning Systems For Dependable Space Applications
        Speaker: Nick Panagiotopoulos (European Space Agency)
    • DFTS: Keynote 1: Secure SoC Development Lifecycle: Challenges and Solutions (Prof. Mark M. Tehranipoor) Salle Louis Armstrong

      Salle Louis Armstrong

      Opening remarks

    • 10:20 AM
      Coffee Break - Gold Sponsor Announcement: Microchip

      Introduction by Kostas Marinis (ESA)

    • DFTS: Session 1: Reliable and Secure Deep Neural Networks Salle Louis Armstrong

      Salle Louis Armstrong

      Opening remarks

      • 21
        Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint Template. Rahul Chaurasia, Abhinav Reddy Asireddy and Anirban Sengupta
      • 22
        EnSAFe: Enabling Sustainable SoC Security Auditing using eFPGA-based Accelerators., Mridha Md Mashahedur Rahman, Shams Tarek, Kimia Zamiri Azar and Farimah Farahmandi
      • 23
        Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes., Alessandro Palumbo, Luca Cassano, Pedro Reviriego and Marco Ottavi
      • 24
        Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses., Alessandro Palumbo, Marco Ottavi and Luca Cassano
      • 25
        An Efficient Security Closure Methodology for EM-based Attacks on Power Grid Structures., Alexandra Takou, Pavlos Stoikos, Moysis Moysis, George Floros, Nestor Evmorfopoulos and Georgios Stamoulis
      • 26
        A Self Aware Security Approach for Real Time Neural Network Applications from Row Hammer Attacks in Multi FPGA Multi User Environment., Krishnendu Guha and Gouriprasad Bhattacharyya
    • Exhibition Espace Gould

      Espace Gould

    • Session 3 - Satellite End-to-end data handling and processing architectures: ESA Missions Auditiorium (TBD)

      Auditiorium (TBD)

      • 27
        Electrical Architecture and Harness Enhancements
        Speaker: Rainer Lang (Airbus Defence and Space GmbH)
      • 28
        High dependability DHS, in orbit operations
        Speaker: JEAN-FRANCOIS SOUCAILLE (AIRBUS DEFENCE AND SPACE)
    • Session 4 - OBDP: Novel Frameworks for On-Board Processing Salle Ella Fitzgerald (145)

      Salle Ella Fitzgerald (145)

      Conveners: Aubrey Dunne (Ubotica Technologies), Dr Maris Tali (ESA)
      • 29
        OBPMark and OBPMark-ML -- On-Board Processing Computational Benchmarks for Space Appliactions and Results
        Speaker: David Steenari (ESA)
      • 30
        A Modular, Reconfigurable and Portable Framework for On-Board Data Processing: Architecture and Applications
        Speaker: Ms Charlotte Crawshaw (Craft Prospect)
      • 31
        The Development of an Onboard Processing Environment within the Flexible and Intelligent Payload Chain Sub-system for Small EO Satellites
        Speaker: Rebecca Davidson (Surrey Satellite Technology Limited)
      • 32
        A novel multi-mission platform for the development of applications, services, and new satellite data algorithms directly in orbit and on-demand, the Italian In-Orbit Space Lab
        Speaker: Dr Vito Fortunato (Planetek Italia)
      • 33
        Insight4EO Architecture to Support Onboard AI Multiapplications from the End-User
        Speaker: Mr Juan Ignacio Bravo Pérez-Villar (Deimos Space)
    • 12:30 PM
      Lunch
    • DFTS: Session 2: Advanced Testing and Validation Techniques Salle Louis Armstrong

      Salle Louis Armstrong

      Opening remarks

      • 34
        An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers., Toshinori Hosokawa, Kyohei Iizuka and Masayoshi Yoshimura
      • 35
        A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and to Improve Gate Exhaustive Fault Coverage., Momona Mizota, Toshinori Hosokawa, Masayoshi Yoshimura and Masayuki Arai
      • 36
        Evaluating the Impact of Aging on Path-Delay Self-Test Libraries., Lorena Anghel, Riccardo Cantoro, Michele Portolan, Sandro Sartoni and Matteo Sonza Reorda
      • 37
        An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing., Yudai Toyooka, Haruki Watanabe, Toshinori Hosokawa and Masayoshi Yoshimura
      • 38
        Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story., Francisco Fuentes, Sergi Alcaide, Raimon Casanova and Jaume Abella.
      • 39
        Partial Triple Modular Redundancy (TMR) Method for Fault-Tolerant Circuit based on HITS Algorithm., Yu Xie, Wen-Yue Yu, Yi-Zhuang Xie and He Chen
      • 40
        Gradient Descent Iterative Correction Unit for Fixed Point Parity Based Codes., Oana Boncalo and Alexandru Amaricai
    • Exhibition Espace Gould

      Espace Gould

    • Session 5 - Satellite End-to-end data handling and processing architectures: ADHA Auditiorium (TBD)

      Auditiorium (TBD)

      • 41
        ADHA Status, Current Activities and Industrial Road Map
        Speakers: Olivier Mourra (ESA-ESTEC- TEC directorate - Head of On-Board Computer & Data Handling Systems Section), David Steenari (ESA)
      • 42
        ADHA System Architecture and Unit Design
        Speaker: Dario Pascucci (Thales Alenia Space)
      • 43
        ADHA - Backplane Definition and Design
        Speakers: Dario Pascucci (Thales Alenia Space), Ms Ketty DE MATTIA
      • 44
        ADHA, an Agile Platform Enhancing New Satellite On-Board Data Processing Systems
        Speakers: Olivier Mourra (ESA-ESTEC- TEC directorate - Head of On-Board Computer & Data Handling Systems Section), David Steenari (ESA), Felix Siegle (ESA-ESTEC)
      • 45
        An Avionics Ecosystem for Small- and Micro-Satellites Based on ADHA 3U Modules
        Speaker: David Steenari (ESA)
    • Session 6 - OBDP: Advances in On-Board Processing for Visual Based Navigation and Monitoring Salle Ella Fitzgerald (TBD)

      Salle Ella Fitzgerald (TBD)

      Convener: Carlos Urbina Ortega (ESA)
      • 46
        Intelligent Space Camera for On-Orbit AI-Driven Visual Monitoring Applications
        Speaker: Dr Aubrey Dunne (Ubotica Technologies)
      • 47
        A synthetic image data generation pipeline for spacecraft fly-by scenarios
        Speaker: Mr Ric Dengel (Tartu Observatory)
      • 48
        ECSS Compliance using Model-Based Design: A Vision-Based Navigation System on an FPGA
        Speaker: Dr Juan Valverde (MathWorks)
      • 49
        Vision Based Lunar Landing using RC64 Rad Hard DSP/ML Manycore Processor
        Speaker: Prof. Ran Ginosar (Ramon Space)
    • 3:40 PM
      Coffee Break
    • DFTS: Session 3: Protecting Accelerators and Microprocessors against hardware attacks Salle Louis Armstrong

      Salle Louis Armstrong

      Opening remarks

      • 50
        Analyzing the Reliability of Alternative Convolution Implementations for Deep Learning Applications., Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Nazzari and Dario Passarello
      • 51
        Uncovering hidden vulnerabilities in DNNs through evolutionary-based Image Test Libraries., Vittorio Turco, Annachiara Ruospo, Gabriele Gavarini, Ernesto Sanchez and Matteo Sonza Reorda
      • 52
        Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator., Salvatore Pappalardo, Ali Piri, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Alberto Bosio and Ernesto Sanchez
      • 53
        Analysis and Improvement of Resilience for Long Short-Term Memory Neural Networks., Mohammad Hasan Ahmadilivani, Jaan Raik, Masoud Daneshtalab and Alar Kuusik
    • Exhibition Espace Gould

      Espace Gould

    • Session 7 - Satellite End-to-end data handling and processing architectures: ADHA Auditiorium (TBD)

      Auditiorium (TBD)

    • Session 8 - OBDP: AI Applications for On-Board FDIR (Failure Detection, Isolation, and Recovery) Salle Ella Fitzgerald (TBD)

      Salle Ella Fitzgerald (TBD)

    • 5:30 PM
      Cocktail - Platinum Sponsor announcement: ISD

      Introduction by Laurent Hili (ESA)

    • DFTS: Keynote 2: Radiation Effects in FPGA and SoCs Salle Louis Armstrong

      Salle Louis Armstrong

      Opening remarks

      Convener: Pierre Maillard (AMD, INc.)
    • Exhibition Espace Gould

      Espace Gould

    • Session 10 - Satellite End-to-end data handling and processing architectures: Industrialisiation Salle Ella Fitzgerald (145)

      Salle Ella Fitzgerald (145)

      • 61
        Unified roadmap for new generation platform DHS
        Speaker: Remi Roques (Airbus)
      • 62
        On-Board Data Handling Architectures, towards integration and modularity.
        Speakers: Mr Francesco Gigliotti (Thales Alenia Space), Mr Mauro De Muro (Thale Alenia Space), Mr Alessandro Marini (Thales Alenia Space)
      • 63
        Flight hardware optimization through modularity and building blocks
        Speaker: Mr Arnaud Wagner (AIRBUS DEFENCE AND SPACE)
      • 64
        Data Center in Space (DCiS)
        Speaker: Prof. Ran Ginosar (Ramon Space)
    • Session 11 - Component Developments for OBDH Systems Salle Sidney Bechet

      Salle Sidney Bechet

    • Session 9 - Satellite End-to-end data handling and processing architectures: RF Salle Miles Davis

      Salle Miles Davis

      • 69
        On-Board Processing for Communication Satellites – Principles and Challenges
        Speaker: Richard Wiest (Airbus Defence and Space GmbH)
      • 70
        SMOS HR Correlator architecture Processing Study
        Speaker: Alexandre MEGE (Airbus Defence and Space)
      • 71
        Accelerated Deep-Learning inference on FPGAs in the Space Domain
        Speaker: Mr Michael Petry (Airbus Defence and Space)
      • 72
        EUFRATE: a High-Perfomance Reconfigurable Architecture for Radiation-hardened Telecom Payloads
        Speaker: Eugenio Scarpa (ARGOTEC SRL)
    • 10:20 AM
      Coffee Break - Gold Sponsor Announcement: Lattice Semiconductor

      Introduction by Gianluca Furano (ESA)

    • DFTS: Session 6: Defects, Errors and Aging Salle Louis Armstrong

      Salle Louis Armstrong

      Opening remarks

      • 73
        Highly Efficient Layered Syndrome-based Double Error Correction Utilizing Current Summing in RRAM Cells to Simplify Decoder, Shruti Dutta, Sai Charan Rachamadugu Chinni, Abhishek Das and Nur Touba
      • 74
        DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture., Raghunandana K K, Yogesh Prasad K R, Matteo Sonza Reorda and Virendra Singh
      • 75
        Image Degradation in Time Due to Interacting Hot Pixels., Glenn Chapman, Li-Yu Wu, Israel Koren, Zahava Koren and Klinsmann J. Coelho Silva Menes
      • 76
        An Estimation Method of Defect Types Using Artificial Neural Networks and Fault Detection Information., Natsuki Ota, Toshinori Hosokawa, Koji Yamazaki, Yukari Yamauchi and Masayuki Arai
      • 77
        An efficient High-Volume Production Performance Screening using On-Chip Ring Oscillators., Tobias Kilian, Abhishek Sengupta, Daniel Tille, Martin Huch and Ulf Schlichtmann
    • Exhibition Espace Gould

      Espace Gould

    • Session 12 - OBDP: RF Salle Miles Davis

      Salle Miles Davis

      • 78
        The Universal Processing Module – Standardised Hardware for State of the Art Radar Data Conversion and Data Processing
        Speaker: Malte Esslinger (Airbus DS - Germany)
      • 79
        A Software Defined Radio for CCSDS 131.2-B protocol: exploiting Graphic Processing Unit accelerator for high performance data reception.
        Speaker: Roberto Ciardi (University of Pisa)
      • 80
        Hardware Accelerated Backprojection Algorithm on UltraScale SoC-FPGA for On-Board SAR Image Formation
        Speaker: Prof. Rui Policarpo Duarte (INESC-ID/ISEL)
      • 81
        Application of AMD Versal Adaptive SoC to Radar Space Time Adaptive Processing and Beamforming Applications in Space
        Speaker: Mr Ken O'Neill (AMD Xilinx)
      • 82
        A Practical Framework to Specify the Prototype Filters for the Analysis of Frequency Stacked Sub-bands
        Speaker: Dr Adem Coskun (ESTEC)
    • Session 13 - Satellite End-to-end data handling and processing architectures: Small- and micro-satellites Salle Ella Fitzgerald (145)

      Salle Ella Fitzgerald (145)

      • 83
        Standardization concepts for CubeSat applications
        Speaker: Tomasz Szewczyk (ESA ESTEC)
      • 84
        An End-To-End Cubesat Data-Processing Chain for Module Development and Validation
        Speaker: Mr Ric Dengel (Tartu Observatory)
      • 85
        COTS GPU Processor Development for On-board Demonstration
        Speaker: Akira Chiba (Mitsubishi Electric Corporation)
      • 86
        Modular Avionics Test Bench
        Speaker: Ran Qedar (Space Products and Innovation GmbH)
    • Session 14 - Radiation Tests and Evaluation for OBDH Systems Salle Sidney Bechet

      Salle Sidney Bechet

      Conveners: Dr Maris Tali (ESA), Melanie Berg (Space R2 LLC)
    • 12:30 PM
      Lunch
    • DFTS: Special Session #1 - Safety and Security Assessment through X-Ray Illumination Salle Louis Armstrong

      Salle Louis Armstrong

      Opening remarks

      • 92
        The use of synchrotron light as an alternative to assess the Single Event Effects induced by Heavy Ions in electronic circuits
      • 93
        Soft-SoC Robustness Evaluation using X-Rays: a Case Study and Differences with other Beams
      • 94
        X ray nanoprobe for fault attacks and circuit edits on 28-nm integrated circuits
      • 95
        Simulation Methodology for Assessing X-Ray Effects on Digital Circuits
    • DFTS: Special Session #3 - Towards AI-based cross-layer resilience: from reliability estimation at design phase to in-field error detection and on-chip sensor data processing Salle Miles Davis

      Salle Miles Davis

      Opening remarks

      • 96
        Challenges in Machine Learning Techniques to Estimate Reliability from Transistors to Circuits
      • 97
        On-Chip Sensors Data Collection and Analysis for SoC Health Management
      • 98
        A Machine Learning-driven EDAC Method for Space-Application Memory
    • Exhibition Espace Gould

      Espace Gould

    • Poster Session Espace Gould

      Espace Gould

      All posters (A0 format) shall be disposed by the presenters before the session in the poster area.

      • 99
        A 22 nm 15 mW AI Accelerator to Enable On-Orbit Neural Network Inference for low-end CubeSats
        Speakers: Mr Bert Boons (Magics Technologies NV), Mr Ehab Ibrahim (Magics Technologies NV), Dr Jaro De Roose (Magics Technologies NV), Mr Ninad Jadhav (Magics Technologies NV), Mr Stijn Hoskens (Magics Technologies NV), Dr Gert Dekkers (Magics Technologies NV), Dr Jasper Wouters (Magics Technologies NV), Dr Ying Cao (Magics Technologies NV)
      • 100
        A fully automated framework to accelerate Deep Learning deployment on edge devices
        Speaker: Federico Fontana (AIKO S.r.l.)
      • 101
        Acinonyx: A Fault-tolerant High-performance Microprocessor in 28-nm FD-SOI for Long-term Space Missions
        Speakers: Mr Mohamed Mounir Mahmoud (KU Leuven), Prof. Jeffrey Prinzie (KU Leuven), Prof. Paul Leroux (KU Leuven)
      • 102
        Characterisation of RFSoC Gen 3 data converters for satellite RF payloads
        Speaker: Mr Magnus Oksbøl Therkelsen (European Space Agency)
      • 103
        CO2M Payload Data Handling Subsystem
        Speakers: Mr Giovanni Battista De Giorgi (OHB), Mr Martin Weinert
      • 104
        ECSS-E-ST-50-15C update - CAN FD evaluation
        Speaker: Alberto Valverde Carretero (ESA)
      • 105
        EDGX-1: A New Frontier in Onboard AI Computing with a Heterogeneous and Neuromorphic Design
        Speaker: Nick Destrycker
      • 106
        Embedded cloud segmentation using AI : Back on years of experiments in orbit on OPS-SAT
        Speaker: Erwann KERVENNIC (IRT Saint Exupéry)
      • 107
        End-to-end data collection, handling and processing for JUICE RPWI LP: from hardware to L1a science data products
        Speaker: Ilona Benko (Swedish Institute of Space Physics)
      • 108
        Error Rate Estimation of DDR4-SDRAM Buffers in Space Mass Memories
        Speakers: Timo Dirkes (DSI Aerospace Technologie GmbH), Christian Spindeldreier (DSI Aerospace Technologie GmbH), Kai Gruermann (DSI Aerospace Technologie GmbH), Jochen Rust (DSI Aerospace Technologie GmbH), Dr Vanessa Wyrwoll (University of Oldenburg)
      • 109
        In Retrospect: Implementing a Custom SpaceWire Driver
        Speaker: Björn Mårtensson (Swedish Institute of Space Physics)
      • 110
        Mytikas demonstration of NG-Ultra with DDR4 for high memory bandwidth
        Speaker: Alexandre MEGE (Airbus Defence and Space)
      • 111
        New rad-hard high frequency PLL synthesizer IC
      • 112
        NG-Ultra Application Development Ecosystem
        Speaker: Marion LE PENVEN
      • 113
        On-board Control Unit for Space Experiments
        Speaker: Rafał Krasa (CBK PAN)
      • 114
        Panorama of Airbus DS Space Products France data handling products and technologies
        Speaker: Benoit Leroy
      • 115
        Payload Computer based on PolarFire SoC
        Speaker: Mr Chedi Fassi (Engineering Minds Munich GmbH)
      • 116
        Performance Evaluation of Space-Grade FPGA Architectures
        Speakers: Dr Christian Spindeldreier (DSI Aerospace Technologie GmbH), Buse Ustaoglu, Ulf Kulau (DSI Aerospace Technologie GmbH), Ole Bischoff, Jochen Rust (DSI Aerospace Technologie GmbH)
      • 117
        Prediction of geomagnetic events from solar wind data using Deep Learning
        Speakers: Enrico Magli, Maurizio Lo Schiavo (Politecnico of Torino), Daniele Telloni (Astrophysical Observatory of Torino), Gianalfredo Nicolini (Astrophysical Observatory of Torino), Silvano Fineschi (Astrophysical Observatory of Torino)
      • 118
        Robust Reconfiguration of Routing Interconnection Network in APSoC Devices
        Speaker: Mostafa Darvishi (Independent Researcher, Polytechnique Montreal Alumni)
      • 119
        Serval: A new chapter of on-board data processing with Versal ACAP-based units
        Speakers: Piotr Kuligowski, Robert Czerwinski
      • 120
        The Radiative Transfer Equation inversion on FPGA. The case of the Photospheric Magnetic field Imager
        Speaker: Dr José M. Morales Fernández (Instituto de Astrofísica de Andalucía (IAA-CSIC) and Spanish Space Solar Physics Consortium)
      • 121
        Towards a Parallel Benchmark for Space Applications: Distributing OBPMark's Image Processing
        Speakers: Mahmoud M. Elbarrawy, Daniel Lüdtke
      • 122
        YPSat’s On-Board Computer & Data Handling
        Speakers: Kevin De Sousa (ESA), Magnus Oksboel Therkelsen (ESA), Suhail Nogd (European Space Agency (ESA))
    • DFTS: Special Session #2 - Reliability of Microcontrollers in Radiation Harsh Environment at Different Levels of Abstraction. The Case Study of the HARV RISC-V SoC Salle Louis Armstrong

      Salle Louis Armstrong

      Opening remarks

      • 123
        Characterization of a Fault-Tolerant RISC-V System-on-Chip for Space Environments
      • 124
        Implementation and Reliability Evaluation of a Vector Extension for a RISC-V System-on-Chip
      • 125
        Hardening a Real-Time Operating System for a Dependable RISC-V System-on-Chip
    • DFTS: Special Session #4 - Resilience of Brain-Inspired Applications: Test and Reliability for Modern ML and AI Hardware Implementations Salle Miles Davis

      Salle Miles Davis

      Opening remarks

      • 126
        Testing and Reliability of Spiking Neural Networks: A Review of the State-of-the-Art
      • 127
        On the resilience of representative and novel data formats in CNNs
      • 128
        Fault tolerance of memristor-based neural networks: a comparative study between formal and spiking neural networks
    • 4:00 PM
      Social Event: Visit of Juan Les Pins + visit Antibes (100 people in total)
    • 7:00 PM
      Gala Cocktail - Espace Méditerranée
    • 8:30 PM
      Gala Dinner + EDHPC/DFTS announcement, Gala Dinner Sponsor announcements: Airbus DS (Mr Laurent BEUGNET) and OHB Systems (Mr Joseph DUNCAN).

      EDHPC/DFTS announcement: Olivier Mourra (ESA), Milena Van Schendel (ESA), Marco Ottavi (University of Twente)

      Introduction of Airbus DS (Gala Dinner Sponsor) by Ali Zadeh (ESA) and presentation of Airbus DS by Mr Laurent BEUGNET (Airbus DS)

      Introduction of OHB Systems (Gala Dinner Sponsor) by Olivier Mourra (ESA) and presentation of OHB Systems by Mr Joseph DUNCAN (OHB Systems)

    • DFTS: Keynote 3: State of the Art of Functional Safety in 2023 Salle Louis Armstrong

      Salle Louis Armstrong

      Opening remarks

      Convener: Dr Mauro Pipponzi
    • Exhibition Espace Gould

      Espace Gould

    • Session 15 - OBDP: Methodologies for On-Board Machine Learning Salle Miles Davis

      Salle Miles Davis

      • 129
        A Hitchhiker’s Guide to Neural Network Design for Onboard Deployment in Space
        Speaker: Wouter Benoot (Edgise)
      • 130
        Efficient In-Orbit CNN Updates
        Speaker: Dr Aubrey Dunne (Ubotica Technologies)
      • 131
        Enhanced Computational Storage Device-based Artificial Intelligence-Triage subsystem
        Speaker: Ms Besma Guesmi (Ubotica)
      • 132
        Low-Precision Floating-Point for Efficient On-Board Deep Neural Network Processing
        Speaker: Mr Cédric GERNIGON (INRIA)
    • Session 16 - OBDH Hardware: New Developments in ICUs & DPUs - Part 1 Salle Ella Fitzgerald (145)

      Salle Ella Fitzgerald (145)

      • 133
        Olympe NG-Ultra based processor board demonstrator test results and lessons learnt
        Speaker: Mr Matthieu Nouard (AIRBUS DEFENCE AND SPACE)
      • 134
        picoRTU-System: Distributed, Modular, Intelligent Remote Terminal Unit System
        Speaker: Jernej Haložan (SkyLabs d.o.o.)
      • 135
        SmallSat payload Control and Data Processing unit
        Speaker: Dr Gerard Rauwerda (Technolution B.V.)
    • Session 17 - Buses, networks & protocols - Part I Salle Sidney Bechet

      Salle Sidney Bechet

      • 136
        Software Based Routing on Satellites - Redundant IP Packet Routing Architecture on Commercial Hardware with Traffic Prioritization
        Speaker: Joshua Schüler (Tesat-Spacecom GmbH & Co. KG)
      • 137
        Photonic Digital Data Handling at Airbus: From High End Definition to Component Technologies
        Speaker: Tania Antonini
      • 138
        Proposal and Investigation of a Next Generation Launcher Communication System Based on Time Sensitive Networking Technology
        Speakers: Mr David Modroño Maeztu (System-on-Chip Engineering S.L. (SoC-e)), Mr Leonardo Favilli (Avio)
      • 139
        SpaceWire/SpaceFibre Analyser Real-Time (SpaceART) system extension to the Wizardlink Protocol
        Speaker: Gionata Benelli (IngeniArs)
    • 10:20 AM
      Coffee Break - Gold Sponsor Announcement: Thales Alenia Space - FR

      Introduction by Olivier Mourra (ESA)

    • DFTS: Session 4: Radiation, Soft Errors and Security Salle Louis Armstrong

      Salle Louis Armstrong

      Opening remarks

      • 140
        Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAs., Kevin Böhmer, Bruno Forlin, Carlo Cazzaniga, Paolo Rech, Gianluca Furano, Nikolaos Alachiotis and Marco Ottavi
      • 141
        Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis., Georgios-Ioannis Paliaroutis, Pelopidas Tsoumanis, Dimitrios Garyfallou, Anastasis Vagenas, Nestor Evmorfopoulos and George Stamoulis
      • 142
        Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis., Christos Georgakidis, Dimitris Valiantzas, Stavros Simoglou, Iordanis Lilitsis, Nikolaos Chatzivangelis, Marko Andjelkovic, Christos Sotiriou and Milos Krstic
      • 143
        On the Prediction of Hardware Security Properties of HLS Designs Using Graph Neural Networks., Amalia-Artemis Koufopoulou, Athanasios Papadimitriou, Aggelos Pikrakis, Mihalis Psarakis and David Hely
      • 144
        QuardTropy: Detecting and Quantifying Unauthorized Information Leakage in Hardware Designs using g-entropy., Hasan Al-Shaikh, Mohammad Bin Monjil, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor and Fahim Rahman
    • Exhibition Espace Gould

      Espace Gould

    • Session 18 - OBDP: Technologies for OBP and AI Inference Acceleration Salle Miles Davis

      Salle Miles Davis

    • Session 19 - OBDH Hardware: New Developments in On-Board Computers (OBCs) Salle Ella Fitzgerald (145)

      Salle Ella Fitzgerald (145)

      • 150
        Third Generation On Board Computer within the Advanced Data & Power Management System
        Speaker: Ruben Willems (Redwire Space)
      • 151
        Amethyst constellation OBC mass production
        Speaker: Jean-Luc Poupat
      • 152
        APSoC: Reconfigurable SoC-based OBC for Future Telecom Applications
        Speaker: Mr Alessandro Avanzi (SITAEL S.p.A.)
      • 153
        OBC-Ultra, the rad-hard NG-Ultra-based On Board Computer for future applications
        Speaker: Mr Adrien Comolet Tirman (AIRBUS DEFENCE AND SPACE)
      • 154
        SpaceWire Based Reconfiguration and Redundancy Management of COTS Based Highly Integrated Onboard Computer
        Speaker: Prem Kumar Hari Krishnan (Evoleo Technologies GmbH)
    • Session 20 - Buses, networks & protocols - Part II Salle Sidney Bechet

      Salle Sidney Bechet

      • 155
        A SpaceFibre Routing Switch for Distributed Payload Processing and Backplane Interconnect
        Speaker: Steve Parkes (STAR-Dundee)
      • 156
        Efficient High Data Rate Networking Using Remote Direct Memory Access Over SpaceFibre
        Speaker: Dave Gibson (STAR-Dundee)
      • 157
        Advanced Ethernet Solutions for Space Applications
        Speaker: Jerome Bourguignon (Microchip Technology Inc.)
      • 158
        Application of SpaceWire and SpaceFibre in GR765
        Speaker: Mr Juan Pedro Cobos
      • 159
        Rad-hard Repeater, Multiplexer and Switch IC for High-Speed Communication
        Speakers: Alp KILIC (Nanoxplore), Edouard Lepape, Kaya Can Akyel (Nanoxplore)
    • 12:30 PM
      Lunch
    • DFTS: Session 5: Applications and Security Salle Louis Armstrong

      Salle Louis Armstrong

      Opening remarks

      • 160
        SASL-JTAG: A Light-Weight Dependable JTAG., Senling Wang, Shaoqi Wei, Jun Ma, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi, Akihiro Shimizu, Xiaoqing Wen and Tianming Ni
      • 161
        A Low-Cost Hardware Accelerator for CCSDS 123 Lossless Hyperspectral Image Compression., Wesley Grignani, Douglas Santos, Luigi Dilillo, Felipe Viel and Douglas Melo
      • 162
        RC-IJTAG: A Methodology for Designing Remotely-Controlled IEEE 1687 Scan Networks., Payam Habiby, Sebastian Huhn and Rolf Drechsler
      • 163
        Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis., Zahin Ibnat, Hadi Mardani Kamali and Farimah Farahmandi
      • 164
        Exploration of System-on-Chip Secure-Boot Vulnerability to Fault-Injection by Side-Channel Analysis., Clément Fanjas, Aboulkassimi Driss, Jessy Clédière and Simon Pontié
    • Exhibition Espace Gould

      Espace Gould

    • Session 21 - OBDP: Technologies for OBP and AI Inference Acceleration Salle Miles Davis

      Salle Miles Davis

      • 165
        High-Level Synthesis-Based On-board Payload Data Processing considering the Roofline Model
        Speaker: Mrs Seungah Lee (Univ Rennes, Inria, CNRS, IRISA, France)
      • 166
        Tradeoff Between Performance and Reliability in FPGA Accelerated DNNs for Space Applications
        Speaker: Dr Dimitris Agiakatsikas (Space Application Services)
      • 167
        Analysis and Implementation of a Space Avionics Co-Processor for Deep Learning Acceleration
        Speaker: David Gonzalez-Arjona (GMV Aerospace and Defence)
      • 168
        Inference and Evaluation of Deep Convolutional Neural Networks on Microchip’s Hardware Accelerator VectorBlox
        Speaker: Pietro Nannipieri (University of Pisa)
      • 169
        Towards the Extension of FPG-AI Toolflow to RNN Deployment on FPGAs for On-board Satellite Applications
    • Session 22 - OBDH Hardware: New Developments in ICUs & DPUs - Part 2 Salle Ella Fitzgerald (145)

      Salle Ella Fitzgerald (145)

      • 170
        The High-Performance Single Board Computer for Space Vehicles
        Speakers: Jonas Lebram (Beyond Gravity, Sweden AB), Mr Vilhelm Geijer (Beyond Gravity Sweden AB)
      • 171
        After six months successful operations in low earth orbit: data processing system architecture and lessons learned from the LisR mission
        Speaker: Konstantin Schäfer
      • 172
        Redundant imaging payload data processing system based on a heterogeneous MPSoC
        Speaker: Clemens Horch (Fraunhofer EMI)
      • 173
        Machine Learning Space Applications using RC64 Rad Hard Manycore Processor
        Speaker: Prof. Ran Ginosar (Ramon Space)
    • Session 23 - Buses, networks & protocols - Part III Salle Sidney Bechet

      Salle Sidney Bechet

      • 174
        A global solution for deterministic SpaceWire / SpaceFibre networks
        Speaker: Dr Vangelis Kollias (TELETEL)
      • 175
        Time Sensitive Networking (TSN) as reliable communications bus for micro-launchers
        Speaker: Carlos Domínguez (GMV)
      • 176
        TESTING ENVIRONMENT DEDICATED FOR TSN DETERMINISTIC NETWORKING BASED ON COTS DEVICES
        Speakers: Henryk Gierszal (Adam Mickiewicz University), Krzysztof Romanowski (ITTI), Mateusz Rajewski, Jarosław Kwiatkowski
      • 177
        IngeniArs IP Cores for on-board high-speed data interfaces
        Speaker: Simone Vagaggini
      • 178
        Model-Based Design and Rapid Prototyping of Distributed Real-Time Applications based on Time-Triggered Ethernet
        Speaker: Dr Ivan Masar (TTTech Computertechnik AG)
    • 3:40 PM
      Coffee Break
    • DFTS: Special Session #5 - Testing, Reliability, and Hardware Security of Computing-in Memories Salle Louis Armstrong

      Salle Louis Armstrong

      Opening remarks

      • 179
        Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability
      • 180
        Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches
      • 181
        Hardware Trojans of Computing-In-Memories: Issues and Methods
    • Exhibition Espace Gould

      Espace Gould

    • Session 24 - OBDP: Technologies for On-Board Compression and Image Processing Salle Miles Davis

      Salle Miles Davis

      • 182
        A hardware/software Design Space Exploration for Efficient Video Compression on ESA missions
        Speaker: Dr Yubal Barrios (Institute of Applied Microelectronics, University of Las Palmas de Gran Canaria)
      • 183
        CCSDS121-based High-Performance Hardware Architecture for Real-Time Data Compression
        Speaker: Mr Samuel Torres-Fau (Institute of Applied Microelectronics, University of Las Palmas de Gran Canaria)
      • 184
        Towards On-Board Image Compression using Vector-Quantized Auto Encoders
        Speaker: Bart Beusen (VITO)
      • 185
        Evaluating the Computational Capabilities of Embedded Multicore and GPU Platforms for On-Board Image Processing
        Speaker: Ivan Rodriguez-Ferrandez (Barcelona Supercomputer Center)
    • Session 25 - OBDH Hardware: New Developments in Mass-Memories Salle Ella Fitzgerald (145)

      Salle Ella Fitzgerald (145)

      • 186
        Architecture Design of a High-Performance Mass Memory Unit based on Xilinx Versal FPGA for Future Space Applications
        Speaker: Christian Spindeldreier (DSI Aerospace Technologie GmbH)
      • 187
        P/L Data Handling and File Management Solution for Sentinel Expansions High Performances Missions
        Speakers: Ms Rita Roscigno (Thales Alenia Space), Mr Silvio Fenu (Thales Alenia Space)
      • 188
        Pelican: Radiation-tolerant Computational Storage
        Speaker: Jason Cerundolo (Zephyr Computing Systems)
      • 189
        Comparing Ext4 and ZFS for Onboard Data Processing: A Systematic Mapping and Experimental Evaluation
        Speakers: Ms Stephanie Liza Johansson (Dependable aerospace Student), Mr Hassan Omer Said (Dependable aerospace system Student), Dr Nandinbaatar Tsog (Embedded engineer at Unibap), Prof. Hakan Forsberg (University professor), Mr Oskar Flordal (Chief Technology Officer at Unibap)
    • Session 26 - Buses, networks & protocols - Part IV Salle Sidney Bechet

      Salle Sidney Bechet

      • 190
        Graph-theoretic Optimizations for Spacecraft Communications Networks
        Speaker: Christopher Rose (Johns Hopkins University Applied Physics Laboratory)
    • DFTS: Closing Session Salle Louis Armstrong

      Salle Louis Armstrong

      Opening remarks

    • Exhibition Espace Gould

      Espace Gould

    • Session 27 - Microelectronics System-on-Chip Processors, Microcontrollers and FPGAs Salle Miles Davis

      Salle Miles Davis

      • 191
        Advancing Toward 7nm FinFET Rad-Hard FPGA for Future Space Applications
        Speakers: Alp KILIC (Nanoxplore), Edouard Lepape
      • 192
        GR765: SPARC and RISC-V Multiprocessor System-on-Chip
        Speaker: Juan Pedro Cobos
      • 193
        Current state and next generation of a systolic array SoC in space
        Speaker: Mr Constantin Papadas (ISD)
      • 194
        The METASAT Hardware Platform: A High-Performance Multicore, AI SIMD and GPU RISC-V Platform for On-board Processing
        Speaker: Dr Leonidas Kosmidis (Barcelona Supercomputing Center)
    • Session 28 - OBDH Hardware: New Developments in ICUs & DPUs - Part 3 Salle Ella Fitzgerald (145)

      Salle Ella Fitzgerald (145)

      • 195
        Case-Study for Integration of COTS SoC Devices in Reliable Space Systems for On-Board Processing
        Speaker: Mr Ivan Rodriguez-Ferrandez (Barcelona Supercomputer Center)
      • 196
        Design of an Edge Computing Space Board through the example of a Reference Design based on Quad ARM® Cortex®-A72 processing module
        Speakers: Thomas Porchez (Teledyne e2v), Wilfrid BERTRAND (Teledyne e2v), Thomas GUILLEMAIN (Teledyne e2v)
      • 197
        Challenges for the board implementation of VERSAL ACAP on a space board
        Speaker: Alexandre MEGE (Airbus Defence and Space)
      • 198
        Versal Space Reference Design : First Design-In Experiences
        Speaker: Rajan Bedi (Spacechips Ltd)
    • Session 29 - Software for On-Board Data Handling and Processing Salle Sidney Bechet

      Salle Sidney Bechet

      • 199
        Applying Model-Based Design and Model-Based Systems Engineering for High-Level Design and Verification in Space Applications
        Speakers: Mr Francisco Javier Moreno (Thales Alenia Space España), Dr Juan Manuel Rodriguez Bejarano (Thales Alenia Space), Mr Raúl Regada Alvarez (Thales Alenia Space)
      • 200
        The Application Software of the Ariel Instrument Control Unit
        Speakers: Dr Sebastiano Ligori (INAF - Osservatorio Astrofisico di Torino), Dr Anna Maria Di Giorgio (Istituto Nazionale di Astrofisica), Dr Leonardo Corcione (Istituto Nazionale di Astrofisica), Dr Vito Capobianco (Istituto Nazionale di Astrofisica), Dr Donata Bonino (Istituto Nazionale di Astrofisica), Dr Focardi Mauro (Istituto Nazionale di Astrofisica), Dr Pace Emanuele (Università degli studi di Firenze)
      • 201
        Spaceflight software validation for future mission applications supported by multicore platforms
        Speaker: Matteo Concas (ESA)
      • 202
        On Board Data Analysis and Realtime Information System
        Speaker: Dr Kurt Schwenk (DLR)
    • 10:20 AM
      Coffee Break
    • Exhibition Espace Gould

      Espace Gould

    • Session 30 - Microelectronics System-on-Chip Processors, Microcontrollers and FPGAs Salle Miles Davis

      Salle Miles Davis

      • 203
        GRLIB: VHDL IP library for fault-tolerant SoC
        Speakers: Fabio Malatesta (Frontgrade Gaisler AB), Mr Martin Rönnbäck (Frontgrade Gaisler)
      • 204
        GR716: LEON3 mixed-signal rad-hard microcontroller
        Speakers: Fabio Malatesta (Frontgrade Gaisler AB), Jan Andersson (Gaisler), Mr Fredrik Johansson (Cobham Gaisler)
      • 205
        Development of the CREOLE ASIC and the Next-Generation On-Board Computer
        Speakers: Mr Lennart Andersson (Beyond Gravity), Mr Vilhelm Geijer (Beyond Gravity), Mr Johas Lebram (Beyond Gravity)
      • 206
        New Space Challenges: Unique Scalable Solutions
        Speaker: Simon Dumortier
    • Session 31 - OBDH Hardware: New Developments in ICUs & DPUs - Part 4 Salle Ella Fitzgerald (145)

      Salle Ella Fitzgerald (145)

      • 207
        NimbleAI: Designing Neuromorphic Sensors to go where Human Eyes can’t
        Speaker: Dr Xabier Iturbe (Ikerlan)
      • 208
        Mechanically Pumped Loop as Heatsink Solution for Advanced Onboard Data Processors
        Speaker: Mr Sybren de Jong (Netherlands Aerospace Centre (NLR))
      • 209
        Self-Calibrating Electronic Controller for Satellite Quantum Entanglement Source
        Speaker: Mr Jacek Goczkowski (Syderal POLSKA / Faculty of Electronics, Telecommunications and Informatics, Gdansk University of Technology)
    • Session 32 - Software for On-Board Data Handling and Processing Salle Sidney Bechet

      Salle Sidney Bechet

      • 210
        A heterogeneous simulation platform with LEON5 and IEEE standard real-time operating system
        Speaker: Mr Daichi Imazato (NEC Space Technologies, Ltd.)
      • 211
        Hardware-Software co-design demonstrator for space applications on a Virtual Platform
        Speakers: Mr Alberto Ferrazzi (Terma), Mattias Holm (Terma), Patricia Lopez Cueva (Thales Alenia Space)
    • 12:10 PM
      Lunch