Speaker
Patrick Gest
(Airbus DS - Germany)
Description
This presentation provides an overview of the use of high-level design and synthesis tools in recent FPGA-based design projects carried out in the logic design department of Airbus D&S Ottobrunn. This includes insights from the work with state-of-the-art tools like the MATLAB HDL Coder and Vitis HLS as they were gained when investigating application scenarios from domains like radar signal processing and AI-based FDIR, as well as combined HW/SW design projects for the latest FPGA-based SoCs.
