Speaker
Adam Taylor
(Adiuvo Engineering and Training Ltd.)
Description
We cannot develop as we have previously done with larger devices, tighter timescales and more functionality demanded. This presentation will introduce a flow which enables model-based design for FPGA, using SYSML the architecture, connectivity, registers and networks can be defined and auto generated to HDL. Enabling the model to be the master, this flow is designed to work with high level tools such as Vitis HLS and Simulink. This approach has been used on two space developments to date to improve the quality of the design and reduce the design time taken, during this presentation examples and deep dive will be provided into these projects.
