Name: Recent Advances in European Space FPGAs: Technologies and Applications
Start: 2024-06-11T09:00:00+02:00
End: 2024-06-11T18:55:00+02:00
Location: Centro Le Benedettine

Recent Advances in European Space FPGAs: Technologies and Applications

Tuesday, 11 June 2024 - 09:00

Monday, 10 June 2024
Tuesday, 11 June 2024

09:00 Welcome Coffee
Welcome Coffee
09:00 - 10:00
10:00 Opening Presentation by University of Pisa - Giovanni Federico Gronchi (University of Pisa) Luca Fanucci (University of Pisa)
Opening Presentation by University of Pisa
- Giovanni Federico Gronchi (University of Pisa)
- Luca Fanucci (University of Pisa)
10:00 - 10:10
10:10 ESA Contribution - David Merodio Codinachs (ESA)
ESA Contribution
- David Merodio Codinachs (ESA)
10:10 - 10:30
10:30 Latest NanoXplore Updates - Jean-Louis FRIGOUL
Latest NanoXplore Updates
- Jean-Louis FRIGOUL
10:30 - 11:10
11:10 CNES Updates - David Dangla (CNES)
CNES Updates
- David Dangla (CNES)
11:10 - 11:20
11:20 Coffee Break
Coffee Break
11:20 - 12:00
12:00 High-Level Synthesis with Bambu: the HERMES Project Experience - Fabrizio Ferrandi (Politecnico di Milano)
High-Level Synthesis with Bambu: the HERMES Project Experience
- Fabrizio Ferrandi (Politecnico di Milano)
12:00 - 12:20
Europe is working on improving competitiveness in the space services sector by developing radiation-resistant, high-performance microprocessors and simplifying the deployment of complex applications. The HERMES project aims to achieve a technology readiness level of 6 for the rad-hard NG-ULTRA FPGA and supports multicore software programming and FPGA acceleration. The presentation will focus on the latest developments and results achieved with the Bambu high-level synthesis tool in the HERMES project. Specifically, it will highlight how Bambu optimizes specific patterns typical in the HERMES use cases.
12:20 Reconfigurable and Rad-Hard Accelerated Computing in Space - Luca Sterpone (Politecnico di Torino)
Reconfigurable and Rad-Hard Accelerated Computing in Space
- Luca Sterpone (Politecnico di Torino)
12:20 - 12:40
Radiation-hardened-by-design (RHBD) reconfigurable devices have gained a lot of attention thanks to their excellent compromise between costs and performance. Being of very limited use due to a lack of performance a few years ago, these devices are now capable of implementing a wide range of applications requiring high computational capabilities. However, to further enhance computing capabilities and permit the effective implementation of Vision-Based Navigation (VBN) algorithms, an ad-hoc HW accelerator able to elaborate multi-dimensional arrays (tensors) is needed. The Tensor Processing Unit (TPU) is an architecture customized for image elaboration algorithms and machine learning. It can manage massive multiplications and additions at high speed with a limited design area and power consumption. Several design strategies investigated the efficient implementation of TPU on FPGA architectures by improving the pipeline strategy and resource sharing towards the TPU processing elements (PEs) or by unifying the tensor computation kernel. In this work, we present the first results achieved with an implementation of a TPU architecture on NG-Medium Radiation-Hardened FPGAs manufactured by NanoXplore.
12:40 FPG-AI: a Technology Independent Framework for Edge AI Deployment Onboard Satellite and its Characterisation on NanoXplore FPGAs - Pietro Nannipieri (University of Pisa)
FPG-AI: a Technology Independent Framework for Edge AI Deployment Onboard Satellite and its Characterisation on NanoXplore FPGAs
- Pietro Nannipieri (University of Pisa)
12:40 - 13:00
The project aims to develop the first AI-to-FPGA toolflow supporting all state-of-the-art FPGAs, including NanoXplore devices. The objective is to facilitate AI deployment onboard satellites and demonstrate the applicability to NanoXplore technology, enhancing European sovereignty. We extended the FPG-AI design for compliance with NanoXplore technology, adding RNNs to the list of supported models and creating a hardware prototype. Results obtained during benchmarking indicate the success of accelerating AI models on rad-hardened FPGAs, reducing development time and cost and increasing performance compared to more advanced HLS approaches.
13:00 Lunch Break
Lunch Break
13:00 - 14:00
14:00 NanoXplore Embedded Software Development - Israel DA COSTA LOPES (Nanoxplore)
NanoXplore Embedded Software Development
- Israel DA COSTA LOPES (Nanoxplore)
14:00 - 14:25
Due to the increasing complexity of current embedded software applications such as Artificial Intelligence, it is indispensable to rely on efficient software development tools for increasing the productivity. To this extent, Nanoxplore provides the NG-ULTRA target platform supporting high-reliability Operating Systems and hypervisor including a baremetal compilation environment. On the top of that, nx-embedded-tools provide a simple and flexible debug and trace approach. This presentation will cover all the layers of the software stack and the toolchain including the associated documentation.
14:25 Discover NX Design Suite Pt 1 - Samah Lahrich
Discover NX Design Suite Pt 1
- Samah Lahrich
14:25 - 15:00
This session aims to present how to use the NX toolchain suite. The purpose of this presentation is to be familiar with advanced features in each step of the flow. Finally, show you how to make a full use of the new GUI.
15:00 Coffee Break
Coffee Break
15:00 - 15:20
15:20 Discover NX Design Suite Pt 2 - Samah Lahrich
Discover NX Design Suite Pt 2
- Samah Lahrich
15:20 - 16:15
This session aims to present how to use the NX toolchain suite. The purpose of this presentation is to be familiar with advanced features in each step of the flow. Finally, show you how to make a full use of the new GUI.
16:15 Cocktail, Thanks and Farewells
Cocktail, Thanks and Farewells
16:15 - 18:15