Recent Advances in European Space FPGAs: Technologies and Applications

Tuesday 11 Jun 2024, 09:00 → 18:55 Europe/Amsterdam

Centro Le Benedettine

NanoXplore and the University of Pisa are proud to present to you the result of their latest collaboration on June 11th 2024: a full day of presentations, Q&A and trainings in regards to the latest news on European Space FPGAs.

 

This conference will teach you all there is to know about the latest advance in European components, FPGAs and SoC FPGAs designed for Space.

 

After a year rich in innovations and breakthroughs, it is the perfect time to hear the results from a large panel of experts and users in presentations by NanoXplore, industry partners and university researchers.

 

In the afternoon, you will also be able to attend to a technical presentation of our SoC products, as well as an entry-level training on our suite of tools: Impulse. 

It is a great occasion to get a leg up on designs and good practices to work with NanoXplore products.

 

It is of course without counting on Q&As with experts, networking with brilliant minds from the Space, the Defense and the Nuclear market, during the event and in the evening in a delicious aperitivo.

 

This year, we also provide the possibility to directly exchange with NanoXplore's best Field Application Engineers, as you will be able to book 20-minutes slots throughout the day with them.

 You will be able to ask you most pressing questions about technical solutions, design principles, debugging options and more!

Get started with your projects directly on the right track thanks to these interviews (The platform will be available at a later date).

 

This exciting event is hosted by the prestigious University of Pisa, one of the oldest of Europe! The gorgeous city of Pisa is not only good for sightseeing and food tasting, but is also easily accessible by train, car or plane, for your convenience. 

 

And what's more, it's completely free! Don't forget to register quickly, as the seats are limited.

 

Registration is required via this website, and an Indico account is required for it (company email address only, not personal one).

To create an Indico account go to the top right corner and choose “Log in”, then “create one here” and follow the given instructions.

After an account has been created you can register using this Indico event site.

 

09:00 Welcome Coffee

1 Opening Presentation by University of Pisa

Speakers: Prof. Giovanni Federico Gronchi (University of Pisa), Prof. Luca Fanucci (University of Pisa)

2 ESA Contribution

Speaker: Mr David Merodio Codinachs (ESA)

3 Latest NanoXplore Updates

Speaker: Mr Jean-Louis FRIGOUL

CompanyOverview.pdf

4 CNES Updates

Speaker: David Dangla (CNES)

11:20 Coffee Break

5 High-Level Synthesis with Bambu: the HERMES Project Experience

Europe is working on improving competitiveness in the space services sector by developing radiation-resistant, high-performance microprocessors and simplifying the deployment of complex applications. The HERMES project aims to achieve a technology readiness level of 6 for the rad-hard NG-ULTRA FPGA and supports multicore software programming and FPGA acceleration.

The presentation will focus on the latest developments and results achieved with the Bambu high-level synthesis tool in the HERMES project. Specifically, it will highlight how Bambu optimizes specific patterns typical in the HERMES use cases.

Speaker: Prof. Fabrizio Ferrandi (Politecnico di Milano)

pisa-bambu.pdf

6 Reconfigurable and Rad-Hard Accelerated Computing in Space

Radiation-hardened-by-design (RHBD) reconfigurable devices have gained a lot of attention thanks to their excellent compromise between costs and performance. Being of very limited use due to a lack of performance a few years ago, these devices are now capable of implementing a wide range of applications requiring high computational capabilities. However, to further enhance computing capabilities and permit the effective implementation of Vision-Based Navigation (VBN) algorithms, an ad-hoc HW accelerator able to elaborate multi-dimensional arrays (tensors) is needed. The Tensor Processing Unit (TPU) is an architecture customized for image elaboration algorithms and machine learning. It can manage massive multiplications and additions at high speed with a limited design area and power consumption. Several design strategies investigated the efficient implementation of TPU on FPGA architectures by improving the pipeline strategy and resource sharing towards the TPU processing elements (PEs) or by unifying the tensor computation kernel. In this work, we present the first results achieved with an implementation of a TPU architecture on NG-Medium Radiation-Hardened FPGAs manufactured by NanoXplore.

Speaker: Prof. Luca Sterpone (Politecnico di Torino)

NX_event_presentation_Polito_v2.pdf

7 FPG-AI: a Technology Independent Framework for Edge AI Deployment Onboard Satellite and its Characterisation on NanoXplore FPGAs

The project aims to develop the first AI-to-FPGA toolflow supporting all state-of-the-art FPGAs, including NanoXplore devices. The objective is to facilitate AI deployment onboard satellites and demonstrate the applicability to NanoXplore technology, enhancing European sovereignty. We extended the FPG-AI design for compliance with NanoXplore technology, adding RNNs to the list of supported models and creating a hardware prototype. Results obtained during benchmarking indicate the success of accelerating AI models on rad-hardened FPGAs, reducing development time and cost and increasing performance compared to more advanced HLS approaches.

Speaker: Dr Pietro Nannipieri (University of Pisa)

NanoXplore Days FPG-AI 11_06_2024v2.pdf

13:00 Lunch Break

8 NanoXplore Embedded Software Development

Due to the increasing complexity of current embedded software applications such as Artificial Intelligence, it is indispensable to rely on efficient software development tools for increasing the productivity. To this extent, Nanoxplore provides the NG-ULTRA target platform supporting high-reliability Operating Systems and hypervisor including a baremetal compilation environment. On the top of that, nx-embedded-tools provide a simple and flexible debug and trace approach. This presentation will cover all the layers of the software stack and the toolchain including the associated documentation.

Speaker: Israel DA COSTA LOPES (Nanoxplore)

240606 NX Embedded Software Development_V4.pdf

9 Discover NX Design Suite Pt 1

This session aims to present how to use the NX toolchain suite. The purpose of this presentation is to be familiar with advanced features in each step of the flow. Finally, show you how to make a full use of the new GUI.

Speaker: Samah Lahrich

240606 Discover_NX_Design_Suite.pdf

15:00 Coffee Break

10 Discover NX Design Suite Pt 2

This session aims to present how to use the NX toolchain suite. The purpose of this presentation is to be familiar with advanced features in each step of the flow. Finally, show you how to make a full use of the new GUI.

Speaker: Samah Lahrich

240606 Discover_NX_Design_Suite.pdf

16:15 Cocktail, Thanks and Farewells