25–27 Mar 2025
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
Draft Agenda published

COTS FPGA technology for On-Board Switching

27 Mar 2025, 11:45
25m
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
Oral presentation Industrial Experiences Industrial Experiences

Speaker

Mr Tomasz Rybak (AROBS Polska)

Description

The main objective of this activity was to perform a technology assessment of Achronix FPGA-based solution for Ethernet layer 2 switch, targeting to meet a data rate up to 100 Gbps per single channel. Assessment consisted of implementation, simulation and breadboard validation using commercially available BittWare VectorPath S7t-VG6 accelerator card, with the Achronix Speedster AC7t1500 FPGA, together with two QSFP loopback devices connected to provide loopback functionality on the Ethernet channels. Additionally, an attempt to transfer achieved solution to Xilinx Versal technology in simulation was made.

Foreseen usage of the outcome of this activity is in the HydRON programme. The main focus of this project was to investigate end-to-end system architecture of a high throughput system (minimum 100 Gbps) that results from combining high data rate optical feeder links, WDM optical ISLs and on-board switching/routing capabilities, needed to implement an optical transport network in space.

Rad Hard / Radiation Tolerant FPGA based solutions currently used in space environment do not meet requirements for the HydRON programme, thus current state-of-the-art COTS FPGA devices have become an attractive solution for telecommunication payload processors for optical transport network in space. Especially with additional features like Network-on-Chip, which allows for high data rate connections inside the FPGA without compromising fabric’s resources for logic and application. FPGA technologies taken into assessment in this project are based on 7 nm lithography process which enables possibility to use them for application cases requiring on-board switching functions with data rates up to 100 Gbps per port, thus meeting the requirements for HydRON.

Affiliation of author(s)

AROBS Polska

Track FPGAs: High Performance

Primary authors

Mr Dawid Linowski (AROBS Polska) Mr Szymon Kałużyński (AROBS Polska) Mr Tomasz Rybak (AROBS Polska)

Presentation materials

There are no materials yet.