Speaker
Description
SRAM-based FPGAs today need high-density configuration memories that are radiation-hardened for space applications. The MNEMOSYNE project aimed to design a radiation-hardened ASIC memory for boot and configuration.
I. RAD-HARD DESIGN:
IMEC designed the analog blocks (LDO, PMU, OSC, IVref, voltage monitors, etc …) using the RH DARE22 platform.
The digital design was done by 3D PLUS, while the physical implementation was performed by IMEC. During that step, radiation hardened techniques were also used:
• Redundancy and restricted cell sets for SEU critical parts.
• High SET immune cells for clock and reset trees
• Glitch filters on strategic nodes
Leakage, an important issue, is greatly reduced in the SOI process compared to bulk technologies. Additionally, this technology allows for body biasing independent of substrate biasing, further reducing leakage.
Finally, derating was used to account for normal device aging and TID impact.
II. MNEMOSYNE TV TESTS RESULTS
For evaluation, the test vehicle underwent TID, SEE, functional, and life tests. For SEE tests, a SEL/SEU LET threshold > 60 MeV.cm²/mg was achieved. These tests confirmed the device's immunity to SEL and revealed low sensitivity to SEU and SEFI. The embedded ECC mitigated all SEU, though some SEFI were observed. A laser SEE test identified the root causes of PMU voltage reference sensitivity. Due to the small technology node and thin gate oxide, TID results showed no significant variation in MOS threshold. Test samples endured TID levels above 100 krad (Si).
The test vehicle passed 1000 hours life test and measurements performed at -55°C, Tamb and +125°C. As for the TID tests, no functional degradation and small drifts in parameter were observed.
Functional tests verify that the memory operates as the boot memory for SRAM-based FPGA using the SPI/QSPI interface. The bypass interface was used due to a controller bug. The tests enabled read operations through the SPI/QSPI interface. The embedded ECC performed as expected, correcting 100% of naturally occurring bit errors. A 128 Mbit ASIC prototype was designed to address issues in the 64 Mbit test vehicle and to add features like a parallel interface.
The tests performed on the 128 Mbit ASIC confirmed the results observed on the former test vehicle with a SEE LET threshold > 85 MeV.cm²/mg.
III PRODUCTS DERIVED FROM MNEMOSYNE
The MNEMOSYNE ASIC is derived in three family lines, using the stacking of multiple 128 Mbit prototype ASIC to achieve higher densities.
MNEMOSYNE 1.8 V: Available in 512 Mbit and 1 Gbit density, supporting SPI, QSPI, OSPI interfaces and designed for the latest FPGAs, MCUs and processors with 1.8 V I/O.
MNEMOSYNE 3.3 V SPI: Available in 512 Mbit and 1 Gbit density, supporting SPI and QSPI interfaces and designed for compatibility with FPGA providing 3.3 V I/Os.
MNEMOSYNE 3.3 V Parallel: Available in 128 Mbit density, supporting EEPROM Protocol and targeting processors and micro-controllers supporting parallel interface and EEPROM protocol.
Each product line is tailored to meet specific requirements, ensuring that the MNEMOSYNE family address a wide range of configuration or boot memory needs.
Affiliation of author(s)
3D PLUS
| Track | Industrial experience |
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