Speaker
Description
Abstract
Developing and deploying a verification methodology can be costly and time consuming. Going without one will be even more costly due to bugs escaping into production hardware systems.
Open Source VHDL Verification Methodology (OSVVM) provides the VHDL community with an already developed, open-source solution. OSVVM implements all of the capabilities of a modern verification methodology: transaction-based testing, a verification framework, verification components, self-checking tests, messaging handling, error tracking, requirements tracking, constrained random testing, scoreboards, functional coverage, co simulation with software, test automation, and a comprehensive set of test reports.
This presentation examines how these capabilities will benefit your projects.
SystemVerilog+UVM also provides a similar set of capabilities. Unfortunately, SV+UVM ended up absurdly complex to use – instead of using a module (entity/architecture in VHDL) with its built-in concurrency, SV+UVM uses OO, sequential code, and fork and join (to get concurrency). As a result, SV has failed to unify the design and verification communities.
VHDL+OSVVM on the other hand uses entity/architectures to create verification components and libraries of subprograms (procedures and functions) to extend VHDL into a complete verification language. In doing this, OSVVM creates verification capabilities that rival SystemVerilog+UVM while at the same time it uses VHDL language elements that are familiar to VHDL design engineers.
As a result, with VHDL+OSVVM and a good verification lead, any VHDL engineer can do verification as well as RTL design.
Benefits
OSVVM + VHDL Provide:
- A structured, transaction based testbench environment in which any VHDL engineer can write VHDL testbenches and test cases for both simple unit/RTL level tests and complex, randomized full chip or system level tests.
- Buzz word features including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering that are simple to use and work like built-in language features.
- Powerful verification data structures that provide unmatched test reporting with HTML for humans and JUnit XML for CI tools.
Author
Jim Lewis is an innovator and leader in the VHDL community. He has 30 plus years of design and teaching experience and is well known within the VHDL community. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, networking, fighter jets, video phones, and space craft.
Whether teaching, developing OSVVM, consulting on VHDL design and verification projects, or working on the IEEE VHDL standard, Mr Lewis brings a deep understanding of VHDL to architect solutions that solve difficult problems in simple ways.
Affiliation of author(s)
SynthWorks Design Inc
| Track | Design Flow |
|---|
