SEFUW: SpacE FPGA Users Workshop, 6th Edition

Session

Verification Flow

26 Mar 2025, 16:00

Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

9. EMLogic AS - Get the right FPGA quality through efficient verification and Requirements Tracking

Espen Tallaksen (EmLogic AS)

26/03/2025, 16:00

Verification flow

Oral presentation

Requirements Tracking (aka Specification coverage) is getting more and more attention, and is critical for space projects. Unfortunately, tracking Verification vs Requirements is often handled manually, which is very time-consuming, error-prone and boring.
**UVVM’s Specification coverage was developed in cooperation with ESA to provide a really efficient solution
to Requirements...

30. Universidad de Sevilla - Towards a Formal Verification Methodology for Digital Electronics in the space sector

Prof. Hipólito Guzmán-Miranda (Universidad de Sevilla)

26/03/2025, 16:25

Verification flow

Oral presentation

With the ever-increasing complexity of digital designs targeting both ASIC and FPGA technologies, the verification gap is not-so-slowly reaching the space sector. Although the space sector has been traditionally driven by rad-hard designs and devices that traded design capabilities and performance for radiation tolerance, recent advances in both microelectronics technology and usage of...

21. SynthWorks Design Inc. - Why Your Team Should be using VHDL + OSVVM for Verification

Jim Lewis (SynthWorks Design Inc.)

26/03/2025, 16:50

Verification flow

Oral presentation

Abstract
Developing and deploying a verification methodology can be costly and time consuming. Going without one will be even more costly due to bugs escaping into production hardware systems.

Open Source VHDL Verification Methodology (OSVVM) provides the VHDL community with an already developed, open-source solution. OSVVM implements all of the capabilities of a modern...