SEFUW: SpacE FPGA Users Workshop, 6th Edition

FPGA IP Cores for Space Applications: A Roadmap for Nanoxplore Platforms

Not scheduled

20m

Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Oral presentation Space Agency Space Agency

Speaker

Mr Sébastien RUFFAT (LGM group)

Description

The LGM Group has been developing IP cores for nearly four years, focusing on sovereign Nanoxplore FPGAs. This presentation will introduce our IP cores designed for DDR2 memory interfacing on NG-MEDIUM and NG-LARGE devices, which are freely available through Nanoxplore’s tools. We will also showcase our research and technological achievements in developing radiation-hardened, “space-ready” DDR2 PL IP cores, incorporating new features for space applications such as memory scrubbing, write-back mechanisms, and low-power operation.

Furthermore, we will discuss our roadmap for the next years, highlighting planned IP core developments including the migration of DDR2 PL IP cores to NG-ULTRA and ULTRA300, the introduction of DDR3 PL IP cores for NG-ULTRA and ULTRA300, and the development of JESD204 IP cores for RF applications.
Finally, we will emphasize LGM's extensive expertise with NanoXplore components and tools, offering tailored solutions based on customer-specific requirements. This includes the development of custom IP cores and complete SoC-FPGA solutions for various NanoXplore SoC-FPGA platforms.

Affiliation of author(s)

LGM group