Speaker
Description
Hyperspectral sensors are playing an increasingly relevant role as part of the space missions payload. They acquire vast amounts of data, which are useful in multiple applications but at the same time are difficult to manage because of the limited capacity of both communication channels and on-board storage. Data compression thus becomes mandatory to reduce raw data volume. And with the latest generations of sensors with increased resolutions, a shift from lossless to lossy compression methods may be needed to achieve required compression ratios.
The Consultative Committee for Space Data Systems (CCSDS) has published several compression standards conceived for space missions. Among them, the CCSDS 123 is aimed at hyperspectral data compression using a predictive approach. Issue 1 focused on lossless compression, while the more recent Issue 2 extends the preprocessing stage to also provide near-lossless compression capabilities, and in addition proposes an alternative entropy coding method, more complex and specifically devised for low-entropy data.
This work presents a new compression IP core fully compliant with the CCSDS-123.0-B-2 compression standard for compression of hyperspectral data in both lossless and near-lossless regimes. The IP core is widely configurable and supports almost every standard feature including all proposed entropy coding methods (sample-adaptive, block-adaptive and hybrid), as well as the most common sample arrangement formats: BIP, BIL and BSQ.
Initially, a design space exploration phase was conducted, which helped us to identify the best strategies to mitigate the data dependencies which are present in the preprocessor datapath. Then, the IP core has been developed as a synthesizable, technology-independent VHDL code. It is built over a previous development, the SHyLoC CCSDS 123-IP core, a hardware implementation of the CCSDS-123.0-B-1 standard. However, a great redesign effort was performed to support near-lossless compression and all new features in a single, flexible architecture which supports all foreseen options, along with an adaptable control which provides a throughput optimized for the dominant data dependencies on each configuration. This allows us to support most of the standard features, while providing a throughput of 1 sample per clock cycle for a subset of the configuration space. The IP core also implements the new Hybrid entropy coder to provide optimal compression ratios in the near-lossless compression regime. This new core reaches clock frequencies of 125 MHz for the Kintex Ultrascale FPGA technology at a moderate usage of logic resources (around 5% LUTs and 13% BRAMs). Implementation results for Microchip and Nanoxplore FPGA devices will also be provided.
The IP core has been developed in the scope of a project funded by ESA with the aim of producing a technology-agnostic reusable core. IUMA leads the project, with participation of DSCAL, UAB and TASIS, who have contributed with the hybrid encoder design, verification and validation, respectively. This new core will join the ESA portfolio of IPs, thus enabling its use as a building block to reduce development costs of future space missions.
Affiliation of author(s)
Institute for Applied Microelectronics - Universidad de Las Palmas de Gran Canaria
European Space Agency
| Track | FPGAs: High Performance |
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