Speakers
Description
The design and verification of FPGA-based systems for space applications rely on complex toolchains that translate high-level logic into hardware implementations. Typically, only a single synthesis, placement, and routing tool is available for a given FPGA, making it difficult to assess how design choices and toolchain behavior interact. The availability of multiple toolchains allows cross-checking of design functionality, and an open-source tool can provide more avenues to inspect and control the implementation process.
To enable this, we have developed an alternative toolchain for the NanoXplore NG-Ultra, the only large, radiation-hardened FPGA made in Europe. As an activity under ESA's OSIP Ideas platform and with help from NanoXplore, we have extended nextpnr to support placement and routing for NG-Ultra. While not a goal of the project, we have also contributed an alternative synthesis flow based on Yosys, which allowed us to target individual aspects of the nextpnr flow when synthesizing test cases during development. The result is a prototype of an almost fully open-source flow, with only the bitstream generation and board programming steps still requiring vendor tools.
This presentation will discuss the technical challenges encountered in developing an alternate open source toolchain while trying not to replicate the vendor's approach. The FPGA’s large size required scaling improvements to the generic architecture-independent parts of nextpnr, while its nontraditional architecture—particularly its routing network—demanded close attention to placement strategies to ensure successful routing. This is a result of both complex routing constraints requiring careful implementation, and an overall limited amount of routing resources relative to logic elements in the NG-Ultra architecture.
Additionally, we will present our validation approach to confirm the correctness of our implementation, and benchmarking results comparing nextpnr against the vendor tool Impulse in terms of routability, resource utilization, and timing. We will explore examples where having an alternative toolchain may give us more confidence in our own design, but also cases where it gives us more flexibility to utilize resources in a different way in order to get specific behavior or test certain capabilities of the tools or the FPGA itself.
Yosys is an open-source framework for register-transfer level (RTL) synthesis, primarily used for digital logic designs written in hardware description languages (HDLs) such as Verilog. It is an essential part of open-source FPGA development workflows, enabling the transformation of high-level hardware designs into low-level representations like gate-level netlists.
Nextpnr is an open-source FPGA place-and-route tool designed to support multiple architectures. It is a key part of the open-source FPGA development ecosystem and it is a tool for converting synthesized netlists into physical configurations for FPGAs.
Affiliation of author(s)
YosysHQ GmbH
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