25–27 Mar 2025
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
Draft Agenda published

KBT Transceiver for Lunar Gateway: FPGA Development and Validation.

27 Mar 2025, 12:10
25m
Newton 1 and 2 (European Space Research and Technology Centre (ESTEC))

Newton 1 and 2

European Space Research and Technology Centre (ESTEC)

Keplerlaan 1 2201AZ Noordwijk ZH The Netherlands
Oral presentation Industrial Experiences Industrial Experiences

Speaker

Francesco Zanaboni

Description

Lunar Gateway is central to the Artemis missions for returning to the Moon for scientific discovery and chart a path for the first human missions to Mars.
This space station will be a multi-purpose outpost supporting lunar surface missions, science in lunar orbit and human exploration further into the cosmos.
Thales Alenia Space has signed a contract with the European Space Agency to develop ESPRIT (European System Providing Refueling, Infrastructure and Telecommunications) for the upcoming lunar space station.
The HLCS (Halo Lunar Communication System), is a fundamental element of ESPRIT, and it provides S-Band and Ka-Band uplink and downlink with search and tracking function.
In the field of communications and tracking, we will focus on the the K-Band Transceiver (KBT), a nodal element of the HLCS subsystem developed by Thales Alenia Space.
The KBT equipment uses a novel System-On-Chip based on the PolarFireRT FPGA from MICROCHIP and implementing the processing features related to the Lunar communications, e.g.:
• SpaceWire interface towards the ESPRIT on-board computer (COM-HUB)
• LDPC coding and decoding functions
• SRRC-OQPSK demodulation up to 50 Msps
• SRRC-OQPSK modulation up to 20 Msps
• FFT on the receiver side and local sweeping on the transmitter side for autonomous establishing of the Lunar link

The KBT SoC embeds the LEON2FT Processor that is in charge of equipment-level management and low rate signal processing tasks. It also includes the “daiFPU” Floating Point Unit (from daiteq s.r.o.) used to implement fine power estimation algorithms as needed for supporting the antenna pointing towards the Lunar asset.
The presentation will provide a thorough overview of the equipment architectural design placing special emphasis on the relevant digital core based on SoC outlined above.

Affiliation of author(s)

Thales Alenia Space

Track FPGAs: High Performance

Primary author

Co-authors

Dario Gelfusa (Thales Alenia Space) David Fiore (Thales Alenia Space Italia) Isaia Martinazzo (Thales Alenia Space) Lorenzo Simone (Thales Alenia Space) Marco Matta (Thales Alenia Space) Mario Frezzini (Thales Alenia Space) Roberto Romanato (Thales Alenia Space)

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