Speaker
Description
Single Event Upsets (SEUs) affecting configuration memory (CRAM) of programmable logic are a main source of faults that eventually lead to the system's failure due to hardware design corruption. The lack of information on how resources are programmed in CRAM significantly limits the ability to develop accurate reliability evaluation methodologies and tailored mitigation strategies, which could benefit from the knowledge of how SEUs can modify a circuit. Additionally, the lack of efficient integration mechanisms with first-party tools inhibits the automatization of radiation testing experiments and robustness evaluation campaigns.
PyXEL is a Python-based toolkit that supports robustness assessment experiments exploiting automatization and CRAM analysis. PyXEL allows the evaluation of netlists and implemented designs through non-invasive fault emulation, acting on the actual device, enabling a fast and accurate analysis based on used resources and emulated faults. PyXEL offers comprehensive reliability analysis techniques, including fine-grained fault injections, specific fault emulation (e.g., open routing, LUT corruption), and fault localization during radiation testing. PyXEL offers techniques and insight not currently available from vendors or third-party tools, assisting the designer in solving the mapping between CRAM and hardware and detecting the most sensitive parts of the design to SEUs while evaluating the overall design robustness. Additionally, PyXEL offers the methodology for visualizing, decoding, and analyzing the configuration data of programmable hardware devices and facilitates the development of mitigation solutions based on customized implementation solutions.
The comprehensive analysis flow supported by PyXEL includes fault model extraction during radiation testing, an assessment of system and module robustness through fault injection campaigns, and support for the implementation of hardening techniques. PyXEL supports the latest AMD devices, such as the 7 Series, Ultrascale, and Ultrascale+.
Affiliation of author(s)
Politecnico di Torino
| Track | Fault Tolerance Methodologies and Tools |
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