Speaker
Description
In recent years, the aerospace industry has increasingly focused on reducing satellite costs and, notably, minimizing Time-To-Market (TTM). IP cores offer an ideal solution by providing pre-validated, reusable modules that simplify the design and development process. By leveraging these ready-made components, engineers can concentrate on system integration and customization, accelerating the creation of reliable, efficient satellite systems while reducing design risks and iterations.
IngeniArs S.r.l., an Italian SME based in Pisa, specializes in delivering cutting-edge products and design services for the aerospace sector. Their extensive portfolio of Intellectual Property (IP) cores, designed for implementation on Field-Programmable Gate Arrays (FPGA) or Application-Specific Integrated Circuits (ASIC), focuses on satellite communications, artificial intelligence, and on-board data handling communication links and networks.
For satellite communications, IngeniArs offers IP cores for both transmitters and receivers that comply with the CCSDS 131.2-B standard, tailored for high-rate Radio Frequency (RF) telemetry applications, primarily in Earth Observation. These cores support all 27 Modulation and Coding (ModCod) formats specified by the standard, enabling Earth-to-Ground communication at rates of up to 1 Gbaud.
IngeniArs has recently expanded its portfolio with two new IP cores for optical Payload Data Transmission (PDT). These cores are fully compliant with the CCSDS 142.0-B standard and support both High Photon Efficiency (HPE) and Optical On-Off Keying (O3K) protocols. They are suitable for Earth-to-Ground communication as well as Inter-Satellite Links (ISL). The HPE core, utilizing an SCPPM encoder, supports transmission rates up to 8 Gbps, while the O3K core, capable of reaching 10 Gbps, offers encoding options with either Low Density Parity Check (LDPC) or Reed-Solomon (RS).
The primary solution in IngeniArs' portfolio for implementing Artificial Intelligence (AI) and Computer Vision (CV) algorithms is the GPU@SAT Soft Core. This core can be implemented on space-qualified FPGAs/ASICs, enabling on-board data processing and handling. It is highly scalable and flexible, offering a configurable number of Computational Unit (CU) cores to meet varying complexity and performance requirements. The GPU@SAT core can be easily configured and used through a standard AXI Bus interface.
Finally, IngeniArs provides several high-speed on-board data handling and communication solutions, particularly those related to ECSS standards like SpaceWire, SpaceFibre, and WizardLink. The SpaceWire CODEC IP Core supports full-duplex communication up to 400 Mbps, while the SpaceWire Router IP Core manages traffic between up to 31 different nodes, handling both SpaceWire and host ports. SpaceFibre CODEC and Router enable much higher transmission speeds, reaching up to 6.25 Gbps per lane, with an overall data rate of 25 Gbps when using 4 lanes. These cores offer features like virtual channels, Quality of Service, 8b/10b coding, and full compatibility with all SerDes. Finally, the WizardLink TLK Equivalent IP Core is designed to replace the Texas Instruments TLK2711 chip in existing designs, specifically for FPGAs equipped with SERDES devices.
Affiliation of author(s)
IngeniArs S.r.l.
| Track | Industrial experience |
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