Speaker
Description
AGGA - Advanced GPS / Galileo ASIC denotes a family of ASICs for processing satellite navigation signals. The development started with AGGA-2 already before the year 2000, and continued with AGGA-3 in 2004 and AGGA-4 in 2010. In 2022 ESA initiated an activity to convert the AGGA-4 ASIC RTL sources to an IP core for a range of FPGAs used in ESA space missions; this work was implemented by daiteq.
The talk will describe the features of the AGGA-4 IP core and the major design choices made during the design process, notably those that significantly improve the performance of DMA transfers of GNSS observables when compared to the AGGA-4 ASIC, and the adoption of the technology mapping library from the LEON2-FT IP core. A special attention will be paid to the validation of the AGGA-4 IP core and the necessary testing infrastructure that was needed to execute the behavioural tests that are part of the VHDL design database in hardware. The talk will conclude with implementation characteristics of the AGGA-4 IP core implemented in current AMD, Microchip and NanoXplore FPGAs.
In addition, the talk will describe newly implemented features that enable cycle-by-cycle debugging of GNSS software - AGGA-4 Debug Support Unit and FT601 based USB-3 Digital Front End with data bandwidth up to 3Gbps.
Affiliation of author(s)
daiteq s.r.o.
| Track | Industrial experience |
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