Speakers
Description
At Thales Alenia Space Italia, implementation of FEC codecs on FPGA in collaboration with ESA and academic institutions dates back various decades [1],[2] and has contributed to CCSDS standards definition [3]. TAS-I has implemented PCCC (Parallel Concatenated Convolutional Codes) and SCCC (Serially Concatenated Convolutional Codes) codecs and, most recently, LDPC.
While the FPGA technology progresses, efficient, high speed design call for optimized usage of different hardware architectures that may favor random access to memory or switch fabrics to implement the belief propagation among processors and the bit-decision nodes. As explained in [4], all the iterative codes after the turbo code invention are implemented by extrinsic information transfer, that can be seen as a belief propagation network: this applies for SCCC, LDPC and PCCC.
The capability to flexibly design hardware codecs for various applications is addressed by in-depth study of the coding solutions and subsequent selection of make or buy of the codec IP core implemented in FPGA.
Recently the various applications call for an in-house control of the codec algorithms for added flexibility (some LDPC are being used in the AWGN channel, as in deep space (ESPRIT) and earth observation applications (PLATINO), others are needed in Binary Symmetric Channels (BSC) as in general BB84 QKD Reconciliation, and some in the Binary Erasure Channel (BEC) as in the ESTOL (ESA Standard for Terabit Optical Links).
Hence, a study group has addressed theoretical, algorithmic studies and hardware design selecting first the most suitable LDPC. The code design is normally based on regular and irregular LDPC, achieved by density evolution [5] techniques and progressive edge growth [6].
At TAS-I, the ESPRIT [7],[8] code has been analyzed and simulated into details; the simulation time has been reduced by tree analysis of the tanner graphs.
The wide set of codes addressed has been also considered for BB84 QKD, considering also techniques in [9].
[1] D.Giancristofaro, V.Piloni, R.Novello, R. Giubilei, J. Tousch: “Performances of Novel DVB-RCS Standard Turbo Code and its Applications in On-Board Processing Satellites”; IEEE EMPS-PIMRC 2000, London, 2000 .
[2] S. Benedetto, C. Berrou, C. Douillard, R. Garello, D. Giancristofaro, A. Ginesi, L. Giugno, M. Luise, G. Montorsi, “MHOMS: High Speed ACM Modem for Satellite Applications”, IEEE Wireless Communications Journal, April 2005.
[3] S.Benedetto, G.Montorsi, A.Ginesi, D.Giancristofaro, M.Fonte: “A Flexible Near-Shannon SCCC Turbo Code for Telemetry Applications”, ESA STR-250, 2005, ESTEC.
[4] EP3622642 B1 - Minimum-Size Belief Propagation Network for FEC Iterative Encoders and Decoders and Related Routing Method.
[5] T. J. Richardson and R. L. Urbanke: “The Capacity of Low-Density Parity-Check Codes Under Message-Passing Decoding”, IEEE on IT, 2001.
[6] X.Y. Hu, E. Elefteriou, D.M. Arnold, “Regular and Irregular Progressive Edge Growth Tanner Graphs”, IEEE on IT, Jan 2005.
[7] TM Synchronization and Channel Coding CCSDS 131.0-B-3
[8] W. H. Zhao, J. P. Long: “Implementing the NASA Deep Space LDPC Codes for Defense Applications”, MILCOM 2013.
[9] E.O. Kiktenko et alii, “Symmetric blind information reconciliation for quantum key distribution”, arXiv:1612.03673v2 [quant-ph] 25 Feb 2019.
Affiliation of author(s)
Università degli studi dell'Aquila, Thales Alenia Space Italia
| Track | Industrial experience |
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