Speaker
Description
We present a Time-to-digital Converter (TDC) implemented on Field-Programmable Gate Array (FPGA) technology that exploits the statistics of single-photon detection to provide the proper input distribution to guarantee bin calibrations during the signal acquisition without any TDC stop or data loss. As a standard solution, TDCs usually integrate a ring-oscillator to provide the input statistics for the calibration. When a new calibration is required, the data acquisition needs to be stop. Our configuration, which we called “steady calibration”, allows to combine the acquisition and the calibration at the same time. The advantage is not only the removal of data loss but also an improvement in the performances of the TDC (i.e., its jitter) as the calibration is carried out every time there is a new detected event. This application is particularly well-suited for Satellite Quantum Communications where single-photon detectors (SPDs) are part of a setup in a harsh environment. As a matter of fact, temperature has a direct effect on the jitter of tapped delay-line TDC. Therefore, temperature changes in space environment can have a major impact on the performances of a TDC.
The TDC, called “Marty” and implemented on a Zynq-7000 chip with an FPGA+CPU architecture based on the one proposed by Stanco et al. (Versatile and Concurrent FPGA-Based Architecture for Practical Quantum Communication Systems doi.org/10.1109/TQE.2022.3143997), has a bin size of ~18ps, an average jitter of ~27 ps (at room temperature) and can sustain up to 15 Mevent/s (transferred via ethernet connection). The device was tested in a two-channel configuration in a dedicated climatic chamber ranging from 5° to 80° to force a relevant change in the jitter performances (the SPD was not inside the chamber). It was verified that the steady calibration not only can guarantee no data loss, but it also prevents jitter to diverge as temperature increases (in our case jitter starts at ~28 ps at 5° and reaches ~32 ps at 80°).
Furthermore, the steady calibration is able to reduce the overall jitter variability bringing to a more stable jitter value with an average standard deviation ⟨σsteady⟩ = 0.64 ps with respect to the non-steadily-calibrated one ⟨σRO⟩ = 1.33 ps. Last, the TDC was also integrated into a Quantum Key Distribution receiver setup and successfully tested for a real QKD implementation, showing its equivalence with a commercial TDC device.
This result can be relevant for future (European) space missions where time-tagging units are required to have stable and low jitter value, in particular for those missions related to critical applications like Quantum Communications or Quantum Random Number Generation where the TDC is a fundamental tool to readout qubits via single-photon detectors.
This work was presented on a pre-print paper (M. R. Bolaños W. et al., A time-to-digital converter with steady calibration through single-photon detection doi.org/10.48550/arXiv.2406.01293) which is currently under review by a scientific journal.
Affiliation of author(s)
Department of Information Engineering, University of Padova, via Gradenigo 6/B, 35131 Padova, Italy
| Track | FPGAs: High Performance |
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